Add more SIMD intrinsics

Author: antoyo

src/intrinsic/llvm.rs

@@ -13,6 +13,11 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(
     func_name: &str,
     original_function_name: Option<&String>,
 ) -> Cow<'b, [RValue<'gcc>]> {
+    // TODO: this might not be a good way to workaround the missing tile builtins.
+    if func_name == "__builtin_trap" {
+        return vec![].into();
+    }
+
     // Some LLVM intrinsics do not map 1-to-1 to GCC intrinsics, so we add the missing
     // arguments here.
     if gcc_func.get_param_count() != args.len() {
@@ -287,7 +292,9 @@ pub fn adjust_intrinsic_arguments<'a, 'b, 'gcc, 'tcx>(
                 new_args.push(last_arg);
                 args = new_args.into();
             }
-            "__builtin_ia32_vfmaddsubps512_mask" | "__builtin_ia32_vfmaddsubpd512_mask" => {
+            "__builtin_ia32_vfmaddsubps512_mask"
+            | "__builtin_ia32_vfmaddsubpd512_mask"
+            | "__builtin_ia32_cmpsh_mask_round" => {
                 let mut new_args = args.to_vec();
                 let last_arg = new_args.pop().expect("last arg");
                 let arg4_type = gcc_func.get_param_type(3);
@@ -1085,6 +1092,17 @@ pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function
         "llvm.x86.avx512.mask.load.pd.512" => "__builtin_ia32_loadapd512_mask",
         "llvm.x86.avx512.mask.load.d.256" => "__builtin_ia32_movdqa32load256_mask",
         "llvm.x86.avx512.mask.load.q.256" => "__builtin_ia32_movdqa64load256_mask",
+        "llvm.x86.avx512fp16.mask.cmp.sh" => "__builtin_ia32_cmpsh_mask_round",
+        "llvm.x86.avx512fp16.vcomi.sh" => "__builtin_ia32_cmpsh_mask_round",
+        // TODO: support the tile builtins:
+        "llvm.x86.ldtilecfg" => "__builtin_trap",
+        "llvm.x86.sttilecfg" => "__builtin_trap",
+        "llvm.x86.tileloadd64" => "__builtin_trap",
+        "llvm.x86.tilerelease" => "__builtin_trap",
+        "llvm.x86.tilestored64" => "__builtin_trap",
+        "llvm.x86.tileloaddt164" => "__builtin_trap",
+        "llvm.x86.tilezero" => "__builtin_trap",
+        "llvm.x86.tdpbf16ps" => "__builtin_trap",
 
         // NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py
         _ => include!("archs.rs"),