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Merge pull request #151 from GuillaumeGomez/x86-intrinsics
Add intrinsic translation for x86 arch
2 parents f537564 + 3970825 commit 0237d95

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‎src/intrinsic/llvm.rs

+7-128
Original file line numberDiff line numberDiff line change
@@ -3,134 +3,13 @@ use gccjit::Function;
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use crate::context::CodegenCx;
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pub fn intrinsic<'gcc, 'tcx>(name: &str, cx: &CodegenCx<'gcc, 'tcx>) -> Function<'gcc> {
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let gcc_name =
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match name {
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"llvm.x86.xgetbv" => "__builtin_ia32_xgetbv",
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// NOTE: this doc specifies the equivalent GCC builtins: http://huonw.github.io/llvmint/llvmint/x86/index.html
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"llvm.x86.sse2.pmovmskb.128" => "__builtin_ia32_pmovmskb128",
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"llvm.x86.avx2.pmovmskb" => "__builtin_ia32_pmovmskb256",
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"llvm.x86.sse2.cmp.pd" => "__builtin_ia32_cmppd",
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"llvm.x86.sse2.movmsk.pd" => "__builtin_ia32_movmskpd",
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"llvm.x86.ssse3.pshuf.b.128" => "__builtin_ia32_pshufb128",
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"llvm.x86.sse2.pause" => "__builtin_ia32_pause",
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"llvm.x86.avx2.pshuf.b" => "__builtin_ia32_pshufb256",
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"llvm.x86.avx2.pslli.d" => "__builtin_ia32_pslldi256",
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"llvm.x86.avx2.psrli.d" => "__builtin_ia32_psrldi256",
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"llvm.x86.sse2.pslli.q" => "__builtin_ia32_psllqi128",
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"llvm.x86.avx.vzeroupper" => "__builtin_ia32_vzeroupper",
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"llvm.x86.avx2.vperm2i128" => "__builtin_ia32_permti256",
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"llvm.x86.avx2.psrli.w" => "__builtin_ia32_psrlwi256",
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"llvm.x86.sse2.storeu.dq" => "__builtin_ia32_storedqu",
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"llvm.x86.sse2.psrli.w" => "__builtin_ia32_psrlwi128",
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"llvm.x86.avx2.pabs.d" => "__builtin_ia32_pabsd256",
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"llvm.x86.sse2.psrli.q" => "__builtin_ia32_psrlqi128",
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"llvm.x86.avx2.pabs.w" => "__builtin_ia32_pabsw256",
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"llvm.x86.avx2.pblendvb" => "__builtin_ia32_pblendvb256",
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"llvm.x86.avx2.pabs.b" => "__builtin_ia32_pabsb256",
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"llvm.x86.avx2.psrli.q" => "__builtin_ia32_psrlqi256",
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"llvm.x86.sse41.pblendvb" => "__builtin_ia32_pblendvb128",
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"llvm.x86.sse41.pblendw" => "__builtin_ia32_pblendw128",
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"llvm.x86.sse42.crc32.32.8" => "__builtin_ia32_crc32qi",
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"llvm.x86.sse42.crc32.32.16" => "__builtin_ia32_crc32hi",
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"llvm.x86.sse42.crc32.32.32" => "__builtin_ia32_crc32si",
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"llvm.x86.sse42.crc32.64.64" => "__builtin_ia32_crc32di",
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"llvm.x86.avx2.pavg.w" => "__builtin_ia32_pavgw256",
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"llvm.x86.avx2.pavg.b" => "__builtin_ia32_pavgb256",
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"llvm.x86.avx2.phadd.w" => "__builtin_ia32_phaddw256",
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"llvm.x86.avx2.phadd.d" => "__builtin_ia32_phaddd256",
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"llvm.x86.avx2.phadd.sw" => "__builtin_ia32_phaddsw256",
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"llvm.x86.avx2.phsub.w" => "__builtin_ia32_phsubw256",
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"llvm.x86.avx2.phsub.d" => "__builtin_ia32_phsubd256",
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"llvm.x86.avx2.phsub.sw" => "__builtin_ia32_phsubsw256",
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"llvm.x86.avx2.gather.d.d" => "__builtin_ia32_gatherd_d",
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"llvm.x86.avx2.gather.d.d.256" => "__builtin_ia32_gatherd_d256",
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"llvm.x86.avx2.gather.d.ps" => "__builtin_ia32_gatherd_ps",
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"llvm.x86.avx2.gather.d.ps.256" => "__builtin_ia32_gatherd_ps256",
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"llvm.x86.avx2.gather.d.q" => "__builtin_ia32_gatherd_q",
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"llvm.x86.avx2.gather.d.q.256" => "__builtin_ia32_gatherd_q256",
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"llvm.x86.avx2.gather.d.pd" => "__builtin_ia32_gatherd_pd",
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"llvm.x86.avx2.gather.d.pd.256" => "__builtin_ia32_gatherd_pd256",
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"llvm.x86.avx2.gather.q.d" => "__builtin_ia32_gatherq_d",
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"llvm.x86.avx2.gather.q.d.256" => "__builtin_ia32_gatherq_d256",
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"llvm.x86.avx2.gather.q.ps" => "__builtin_ia32_gatherq_ps",
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"llvm.x86.avx2.gather.q.ps.256" => "__builtin_ia32_gatherq_ps256",
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"llvm.x86.avx2.gather.q.q" => "__builtin_ia32_gatherq_q",
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"llvm.x86.avx2.gather.q.q.256" => "__builtin_ia32_gatherq_q256",
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"llvm.x86.avx2.gather.q.pd" => "__builtin_ia32_gatherq_pd",
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"llvm.x86.avx2.gather.q.pd.256" => "__builtin_ia32_gatherq_pd256",
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"llvm.x86.avx2.pmadd.wd" => "__builtin_ia32_pmaddwd256",
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"llvm.x86.avx2.pmadd.ub.sw" => "__builtin_ia32_pmaddubsw256",
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"llvm.x86.avx2.maskload.d" => "__builtin_ia32_maskloadd",
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"llvm.x86.avx2.maskload.d.256" => "__builtin_ia32_maskloadd256",
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"llvm.x86.avx2.maskload.q" => "__builtin_ia32_maskloadq",
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"llvm.x86.avx2.maskload.q.256" => "__builtin_ia32_maskloadq256",
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"llvm.x86.avx2.maskstore.d" => "__builtin_ia32_maskstored",
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"llvm.x86.avx2.maskstore.d.256" => "__builtin_ia32_maskstored256",
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"llvm.x86.avx2.maskstore.q" => "__builtin_ia32_maskstoreq",
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"llvm.x86.avx2.maskstore.q.256" => "__builtin_ia32_maskstoreq256",
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"llvm.x86.avx2.pmaxs.w" => "__builtin_ia32_pmaxsw256",
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"llvm.x86.avx2.pmaxs.d" => "__builtin_ia32_pmaxsd256",
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"llvm.x86.avx2.pmaxs.b" => "__builtin_ia32_pmaxsb256",
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"llvm.x86.avx2.pmaxu.w" => "__builtin_ia32_pmaxuw256",
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"llvm.x86.avx2.pmaxu.d" => "__builtin_ia32_pmaxud256",
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"llvm.x86.avx2.pmaxu.b" => "__builtin_ia32_pmaxub256",
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"llvm.x86.avx2.pmins.w" => "__builtin_ia32_pminsw256",
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"llvm.x86.avx2.pmins.d" => "__builtin_ia32_pminsd256",
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"llvm.x86.avx2.pmins.b" => "__builtin_ia32_pminsb256",
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"llvm.x86.avx2.pminu.w" => "__builtin_ia32_pminuw256",
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"llvm.x86.avx2.pminu.d" => "__builtin_ia32_pminud256",
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"llvm.x86.avx2.pminu.b" => "__builtin_ia32_pminub256",
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"llvm.x86.avx2.mpsadbw" => "__builtin_ia32_mpsadbw256",
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"llvm.x86.avx2.pmul.dq" => "__builtin_ia32_pmuldq256",
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"llvm.x86.avx2.pmulu.dq" => "__builtin_ia32_pmuludq256",
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"llvm.x86.avx2.pmulh.w" => "__builtin_ia32_pmulhw256",
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"llvm.x86.avx2.pmulhu.w" => "__builtin_ia32_pmulhuw256",
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"llvm.x86.avx2.pmul.hr.sw" => "__builtin_ia32_pmulhrsw256",
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"llvm.x86.avx2.packsswb" => "__builtin_ia32_packsswb256",
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"llvm.x86.avx2.packssdw" => "__builtin_ia32_packssdw256",
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"llvm.x86.avx2.packuswb" => "__builtin_ia32_packuswb256",
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"llvm.x86.avx2.packusdw" => "__builtin_ia32_packusdw256",
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"llvm.x86.avx2.permd" => "__builtin_ia32_permvarsi256",
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"llvm.x86.avx2.permps" => "__builtin_ia32_permvarsf256",
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"llvm.x86.avx2.psad.bw" => "__builtin_ia32_psadbw256",
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"llvm.x86.avx2.psign.w" => "__builtin_ia32_psignw256",
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"llvm.x86.avx2.psign.d" => "__builtin_ia32_psignd256",
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"llvm.x86.avx2.psign.b" => "__builtin_ia32_psignb256",
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"llvm.x86.avx2.psll.w" => "__builtin_ia32_psllw256",
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"llvm.x86.avx2.psll.d" => "__builtin_ia32_pslld256",
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"llvm.x86.avx2.psll.q" => "__builtin_ia32_psllq256",
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"llvm.x86.avx2.pslli.w" => "__builtin_ia32_psllwi256",
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"llvm.x86.avx2.pslli.q" => "__builtin_ia32_psllqi256",
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"llvm.x86.avx2.psllv.d" => "__builtin_ia32_psllv4si",
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"llvm.x86.avx2.psllv.d.256" => "__builtin_ia32_psllv8si",
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"llvm.x86.avx2.psllv.q" => "__builtin_ia32_psllv2di",
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"llvm.x86.avx2.psllv.q.256" => "__builtin_ia32_psllv4di",
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"llvm.x86.avx2.psra.w" => "__builtin_ia32_psraw256",
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"llvm.x86.avx2.psra.d" => "__builtin_ia32_psrad256",
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"llvm.x86.avx2.psrai.w" => "__builtin_ia32_psrawi256",
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"llvm.x86.avx2.psrai.d" => "__builtin_ia32_psradi256",
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"llvm.x86.avx2.psrav.d" => "__builtin_ia32_psrav4si",
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"llvm.x86.avx2.psrav.d.256" => "__builtin_ia32_psrav8si",
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"llvm.x86.avx2.psrl.w" => "__builtin_ia32_psrlw256",
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"llvm.x86.avx2.psrl.d" => "__builtin_ia32_psrld256",
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"llvm.x86.avx2.psrl.q" => "__builtin_ia32_psrlq256",
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"llvm.x86.avx2.psrlv.d" => "__builtin_ia32_psrlv4si",
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"llvm.x86.avx2.psrlv.d.256" => "__builtin_ia32_psrlv8si",
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"llvm.x86.avx2.psrlv.q" => "__builtin_ia32_psrlv2di",
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"llvm.x86.avx2.psrlv.q.256" => "__builtin_ia32_psrlv4di",
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"llvm.x86.sse.sqrt.ss" => "__builtin_ia32_sqrtss",
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"llvm.x86.pclmulqdq" => "__builtin_ia32_pclmulqdq128",
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"llvm.x86.sha1msg1" => "__builtin_ia32_sha1msg1",
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"llvm.x86.sha1msg2" => "__builtin_ia32_sha1msg2",
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"llvm.x86.sha1nexte" => "__builtin_ia32_sha1nexte",
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"llvm.x86.sha1rnds4" => "__builtin_ia32_sha1rnds4",
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"llvm.x86.sha256msg1" => "__builtin_ia32_sha256msg1",
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"llvm.x86.sha256msg2" => "__builtin_ia32_sha256msg2",
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"llvm.x86.sha256rnds2" => "__builtin_ia32_sha256rnds2",
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"llvm.sqrt.v2f64" => "__builtin_ia32_sqrtpd",
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_ => unimplemented!("***** unsupported LLVM intrinsic {}", name),
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};
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let gcc_name = match name {
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"llvm.x86.xgetbv" => "__builtin_ia32_xgetbv",
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// NOTE: this doc specifies the equivalent GCC builtins: http://huonw.github.io/llvmint/llvmint/x86/index.html
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"llvm.sqrt.v2f64" => "__builtin_ia32_sqrtpd",
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// NOTE: this file is generated by https://github.com/GuillaumeGomez/llvmint/blob/master/generate_list.py
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_ => include!("x86.rs"),
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};
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let func = cx.context.get_target_builtin_function(gcc_name);
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cx.functions.borrow_mut().insert(gcc_name.to_string(), func);

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