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Fix riscv inline asm implementation #1306

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bjorn3 opened this issue Dec 13, 2022 · 1 comment
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Fix riscv inline asm implementation #1306

bjorn3 opened this issue Dec 13, 2022 · 1 comment
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C-bug Category: This is a bug. O-riscv Target: RISC-V architecture

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bjorn3 commented Dec 13, 2022

It currently doesn't correctly adjust the stack pointer to account for saved registers.
@bjorn3 bjorn3 added O-riscv Target: RISC-V architecture C-bug Category: This is a bug. labels Dec 13, 2022
@bjorn3 bjorn3 mentioned this issue Feb 5, 2023
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bjorn3 commented Oct 21, 2023 •
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Implemented in https://github.com/bjorn3/rustc_codegen_cranelift/pull/1398

@bjorn3 bjorn3 closed this as completed Oct 21, 2023
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C-bug Category: This is a bug. O-riscv Target: RISC-V architecture
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