Improve lane_type_and_count

Author: bjorn3

src/intrinsics/llvm.rs

@@ -36,7 +36,7 @@ pub fn codegen_llvm_intrinsic_call<'tcx>(
 
         // Used by `_mm_movemask_epi8` and `_mm256_movemask_epi8`
         llvm.x86.sse2.pmovmskb.128 | llvm.x86.avx2.pmovmskb | llvm.x86.sse2.movmsk.pd, (c a) {
-            let (lane_layout, lane_count) = lane_type_and_count(fx, a.layout(), intrinsic);
+            let (lane_layout, lane_count) = lane_type_and_count(fx.tcx, a.layout());
             let lane_ty = fx.clif_type(lane_layout.ty).unwrap();
             assert!(lane_count <= 32);
 

src/intrinsics/mod.rs

@@ -127,20 +127,19 @@ macro atomic_minmax($fx:expr, $cc:expr, <$T:ident> ($ptr:ident, $src:ident) -> $
     $ret.write_cvalue($fx, ret_val);
 }
 
-fn lane_type_and_count<'tcx>(
-    fx: &FunctionCx<'_, 'tcx, impl Backend>,
+pub fn lane_type_and_count<'tcx>(
+    tcx: TyCtxt<'tcx>,
     layout: TyLayout<'tcx>,
-    intrinsic: &str,
 ) -> (TyLayout<'tcx>, u32) {
     assert!(layout.ty.is_simd());
     let lane_count = match layout.fields {
         layout::FieldPlacement::Array { stride: _, count } => u32::try_from(count).unwrap(),
-        _ => panic!(
-            "Non vector type {:?} passed to or returned from simd_* intrinsic {}",
-            layout.ty, intrinsic
-        ),
+        _ => unreachable!("lane_type_and_count({:?})", layout),
     };
-    let lane_layout = layout.field(fx, 0);
+    let lane_layout = layout.field(&ty::layout::LayoutCx {
+        tcx,
+        param_env: ParamEnv::reveal_all(),
+    }, 0).unwrap();
     (lane_layout, lane_count)
 }
 
@@ -161,8 +160,8 @@ fn simd_for_each_lane<'tcx, B: Backend>(
     assert_eq!(x.layout(), y.layout());
     let layout = x.layout();
 
-    let (lane_layout, lane_count) = lane_type_and_count(fx, layout, intrinsic);
-    let (ret_lane_layout, ret_lane_count) = lane_type_and_count(fx, ret.layout(), intrinsic);
+    let (lane_layout, lane_count) = lane_type_and_count(fx.tcx, layout);
+    let (ret_lane_layout, ret_lane_count) = lane_type_and_count(fx.tcx, ret.layout());
     assert_eq!(lane_count, ret_lane_count);
 
     for lane in 0..lane_count {

src/intrinsics/simd.rs

@@ -21,8 +21,8 @@ pub fn codegen_simd_intrinsic_call<'tcx>(
         };
 
         simd_cast, (c a) {
-            let (lane_layout, lane_count) = lane_type_and_count(fx, a.layout(), intrinsic);
-            let (ret_lane_layout, ret_lane_count) = lane_type_and_count(fx, ret.layout(), intrinsic);
+            let (lane_layout, lane_count) = lane_type_and_count(fx.tcx, a.layout());
+            let (ret_lane_layout, ret_lane_count) = lane_type_and_count(fx.tcx, ret.layout());
             assert_eq!(lane_count, ret_lane_count);
 
             let ret_lane_ty = fx.clif_type(ret_lane_layout.ty).unwrap();
@@ -65,8 +65,8 @@ pub fn codegen_simd_intrinsic_call<'tcx>(
             assert_eq!(x.layout(), y.layout());
             let layout = x.layout();
 
-            let (lane_type, lane_count) = lane_type_and_count(fx, layout, intrinsic);
-            let (ret_lane_type, ret_lane_count) = lane_type_and_count(fx, ret.layout(), intrinsic);
+            let (lane_type, lane_count) = lane_type_and_count(fx.tcx, layout);
+            let (ret_lane_type, ret_lane_count) = lane_type_and_count(fx.tcx, ret.layout());
 
             assert_eq!(lane_type, ret_lane_type);
             assert_eq!(n, ret_lane_count);
@@ -124,7 +124,7 @@ pub fn codegen_simd_intrinsic_call<'tcx>(
             };
 
             let idx = idx_const.val.try_to_bits(Size::from_bytes(4 /* u32*/)).expect(&format!("kind not scalar: {:?}", idx_const));
-            let (_lane_type, lane_count) = lane_type_and_count(fx, v.layout(), intrinsic);
+            let (_lane_type, lane_count) = lane_type_and_count(fx.tcx, v.layout());
             if idx >= lane_count.into() {
                 fx.tcx.sess.span_fatal(fx.mir.span, &format!("[simd_extract] idx {} >= lane_count {}", idx, lane_count));
             }