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Implement SHA256 intrinsics using inline asm
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src/intrinsics/llvm_x86.rs

+84
Original file line numberDiff line numberDiff line change
@@ -910,6 +910,90 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>(
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);
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}
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"llvm.x86.sha256rnds2" => {
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// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sha256rnds2_epu32&ig_expand=5977
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intrinsic_args!(fx, args => (a, b, k); intrinsic);
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let a = a.load_scalar(fx);
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let b = b.load_scalar(fx);
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let k = k.load_scalar(fx);
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codegen_inline_asm_inner(
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fx,
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&[InlineAsmTemplatePiece::String("sha256rnds2 xmm1, xmm2".to_string())],
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&[
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CInlineAsmOperand::InOut {
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reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::xmm1)),
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_late: true,
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in_value: a,
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out_place: Some(ret),
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},
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CInlineAsmOperand::In {
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reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::xmm2)),
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value: b,
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},
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// Implicit argument to the sha256rnds2 instruction
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CInlineAsmOperand::In {
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reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::xmm0)),
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value: k,
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},
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],
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InlineAsmOptions::NOSTACK | InlineAsmOptions::PURE | InlineAsmOptions::NOMEM,
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);
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}
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"llvm.x86.sha256msg1" => {
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// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sha256msg1_epu32&ig_expand=5975
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intrinsic_args!(fx, args => (a, b); intrinsic);
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let a = a.load_scalar(fx);
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let b = b.load_scalar(fx);
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codegen_inline_asm_inner(
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fx,
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&[InlineAsmTemplatePiece::String("sha256msg1 xmm1, xmm2".to_string())],
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&[
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CInlineAsmOperand::InOut {
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reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::xmm1)),
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_late: true,
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in_value: a,
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out_place: Some(ret),
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},
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CInlineAsmOperand::In {
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reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::xmm2)),
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value: b,
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},
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],
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InlineAsmOptions::NOSTACK | InlineAsmOptions::PURE | InlineAsmOptions::NOMEM,
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);
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}
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"llvm.x86.sha256msg2" => {
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// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sha256msg2_epu32&ig_expand=5976
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intrinsic_args!(fx, args => (a, b); intrinsic);
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let a = a.load_scalar(fx);
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let b = b.load_scalar(fx);
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codegen_inline_asm_inner(
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fx,
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&[InlineAsmTemplatePiece::String("sha256msg2 xmm1, xmm2".to_string())],
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&[
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CInlineAsmOperand::InOut {
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reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::xmm1)),
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_late: true,
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in_value: a,
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out_place: Some(ret),
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},
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CInlineAsmOperand::In {
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reg: InlineAsmRegOrRegClass::Reg(InlineAsmReg::X86(X86InlineAsmReg::xmm2)),
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value: b,
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},
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],
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InlineAsmOptions::NOSTACK | InlineAsmOptions::PURE | InlineAsmOptions::NOMEM,
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);
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}
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"llvm.x86.avx.ptestz.256" => {
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// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_testz_si256&ig_expand=6945
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intrinsic_args!(fx, args => (a, b); intrinsic);

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