[WIP] Store vectors in registers

Author: bjorn3

src/analyze.rs

@@ -11,7 +11,7 @@ pub enum SsaKind {
 
 pub fn analyze(fx: &FunctionCx<'_, '_, impl Backend>) -> IndexVec<Local, SsaKind> {
     let mut flag_map = fx.mir.local_decls.iter().map(|local_decl| {
-        if fx.clif_type(local_decl.ty).is_some() {
+        if fx.clif_type(fx.monomorphize(&local_decl.ty)).is_some() {
             SsaKind::Ssa
         } else {
             SsaKind::NotSsa

src/common.rs

@@ -65,6 +65,14 @@ pub fn clif_type_from_ty<'tcx>(tcx: TyCtxt<'tcx>, ty: Ty<'tcx>) -> Option<types:
                 pointer_ty(tcx)
             }
         }
+        _ if ty.is_simd() => {
+            let (lane_type, lane_count) = crate::intrinsics::lane_type_and_count(
+                tcx,
+                tcx.layout_of(ParamEnv::reveal_all().and(ty)).unwrap(),
+            );
+            let lane_type = clif_type_from_ty(tcx, lane_type.ty)?;
+            lane_type.by(u16::try_from(lane_count).unwrap()).expect("SIMD type with more than 255 lanes???")
+        }
         ty::Param(_) => bug!("ty param {:?}", ty),
         _ => return None,
     })

src/lib.rs

@@ -257,6 +257,7 @@ fn build_isa(sess: &Session, enable_pic: bool) -> Box<dyn isa::TargetIsa + 'stat
         flags_builder.set("is_pic", "false").unwrap();
     }
     flags_builder.set("probestack_enabled", "false").unwrap(); // __cranelift_probestack is not provided
+    flags_builder.set("enable_simd", "true").unwrap();
     flags_builder
         .set(
             "enable_verifier",
@@ -286,9 +287,12 @@ fn build_isa(sess: &Session, enable_pic: bool) -> Box<dyn isa::TargetIsa + 'stat
 
     let target_triple = crate::target_triple(sess);
     let flags = settings::Flags::new(flags_builder);
-    cranelift_codegen::isa::lookup(target_triple)
-        .unwrap()
-        .finish(flags)
+
+    let mut isa_builder = cranelift_codegen::isa::lookup(target_triple).unwrap();
+    isa_builder.enable("skylake").unwrap();
+    // FIXME set all enabled rust target features
+
+    isa_builder.finish(flags)
 }
 
 /// This is the entrypoint for a hot plugged rustc_codegen_cranelift

src/pointer.rs

@@ -129,7 +129,16 @@ impl Pointer {
             PointerBase::Stack(stack_slot) => if ty == types::I128 || ty.is_vector() {
                 // WORKAROUND for stack_load.i128 and stack_load.iXxY not being implemented
                 let base_addr = fx.bcx.ins().stack_addr(fx.pointer_type, stack_slot, 0);
-                fx.bcx.ins().load(ty, flags, base_addr, self.offset)
+                /*if ty.is_vector() {
+                    let zero = fx.bcx.ins().iconst(ty.lane_type(), 0);
+                    let vec = fx.bcx.ins().splat(ty, zero);
+                    (0..u8::try_from(ty.lane_count()).unwrap()).fold(vec, |vec, idx| {
+                        let lane = fx.bcx.ins().load(ty.lane_type(), flags, base_addr, self.offset.try_add_i64(i64::from(idx) * i64::from(ty.lane_type().bytes())).unwrap());
+                        fx.bcx.ins().insertlane(vec, idx, lane)
+                    })
+                } else {*/
+                    fx.bcx.ins().load(ty, flags, base_addr, self.offset)
+                //}
             } else {
                 fx.bcx.ins().stack_load(ty, stack_slot, self.offset)
             }