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lines changedSubmodule llvm-project updated 23 files
- llvm/include/llvm/CodeGen/MachineBasicBlock.h+11
- llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp+4-1
- llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp+77-21
- llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.cpp+7
- llvm/lib/Target/RISCV/MCTargetDesc/RISCVAsmBackend.h+1
- llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFObjectWriter.cpp+2
- llvm/lib/Target/RISCV/MCTargetDesc/RISCVFixupKinds.h+3
- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCCodeEmitter.cpp+3
- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.cpp+6-1
- llvm/lib/Target/RISCV/MCTargetDesc/RISCVMCExpr.h+4-3
- llvm/lib/Target/RISCV/RISCVExpandPseudoInsts.cpp+80
- llvm/lib/Target/RISCV/RISCVISelLowering.cpp+67-41
- llvm/lib/Target/RISCV/RISCVISelLowering.h+4
- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp+2
- llvm/lib/Target/RISCV/RISCVInstrInfo.td+5-1
- llvm/lib/Target/RISCV/RISCVMCInstLower.cpp+9
- llvm/lib/Target/RISCV/Utils/RISCVBaseInfo.h+2
- llvm/test/CodeGen/RISCV/codemodel-lowering.ll+80
- llvm/test/CodeGen/RISCV/pic-models.ll+85
- llvm/test/MC/RISCV/relocations.s+34
- llvm/test/MC/RISCV/rv32i-invalid.s+6-6
- llvm/test/MC/RISCV/rvi-pseudos-invalid.s+22
- llvm/test/MC/RISCV/rvi-pseudos.s+47-2
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