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Jorge Aparicio
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add +d16 and +fp-only-sp to thumbv7em-none-eabihf and documentation
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src/librustc_back/target/thumb_base.rs

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// option. This file may not be copied, modified, or distributed
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// except according to those terms.
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// These 4 `thumbv*` targets cover the ARM Cortex-M family of processors which are widely used in
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// microcontrollers. Namely, all these processors:
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//
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// - Cortex-M0
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// - Cortex-M0+
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// - Cortex-M1
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// - Cortex-M3
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// - Cortex-M4(F)
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// - Cortex-M7(F)
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//
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// We have opted for 4 targets instead of one target per processor (e.g. `cortex-m0`, `cortex-m3`,
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// etc) because the differences between some processors like the cortex-m0 and cortex-m1 are almost
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// non-existent from the POV of codegen so it doesn't make sense to have separate targets for them.
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// And if differences exist between two processors under the same target, rustc flags can be used to
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// optimize for one processor or the other.
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//
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// Also, we have not chosen a single target (`arm-none-eabi`) like GCC does because this makes
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// difficult to integrate Rust code and C code. Targeting the Cortex-M4 requires different gcc flags
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// than the ones you would use for the Cortex-M0 and with a single target it'd be impossible to
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// differentiate one processor from the other.
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//
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// About arm vs thumb in the name. The Cortex-M devices only support the Thumb instruction set,
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// which is more compact (higher code density), and not the ARM instruction set. That's why LLVM
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// triples use thumb instead of arm. We follow suit because having thumb in the name let us
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// differentiate these targets from our other `arm(v7)-*-*-gnueabi(hf)` targets in the context of
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// build scripts / gcc flags.
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use target::TargetOptions;
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use std::default::Default;
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pub fn opts() -> TargetOptions {
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// See rust-lang/rfcs#1645 for a discussion about these defaults
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TargetOptions {
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executables: true,
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// In 99%+ of cases, we want to use the `arm-none-eabi-gcc` compiler (there aren't many
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// options around)
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linker: "arm-none-eabi-gcc".to_string(),
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// Because these devices have very little resources having an unwinder is too onerous so we
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// default to "abort" because the "unwind" strategy is very rare.
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panic_strategy: "abort".to_string(),
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// Similarly, one almost always never wants to use relocatable code because of the extra
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// costs it involves.
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relocation_model: "static".to_string(),
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.. Default::default()
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}

src/librustc_back/target/thumbv6m_none_eabi.rs

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// option. This file may not be copied, modified, or distributed
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// except according to those terms.
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// Targets the Cortex-M0, Cortex-M0+ and Cortex-M1 processors (ARMv6-M architecture)
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use target::{Target, TargetOptions, TargetResult};
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pub fn target() -> TargetResult {

src/librustc_back/target/thumbv7em_none_eabi.rs

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// option. This file may not be copied, modified, or distributed
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// except according to those terms.
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// Targets the Cortex-M4 and Cortex-M7 processors (ARMv7E-M)
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//
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// This target assumes that the device doesn't have a FPU (Floating Point Unit) and lowers all the
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// floating point operations to software routines (intrinsics).
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//
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// As such, this target uses the "soft" calling convention (ABI) where floating point values are
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// passed to/from subroutines via general purpose registers (R0, R1, etc.).
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//
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// To opt-in to hardware accelerated floating point operations, you can use, for example,
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// `-C target-feature=+vfp4` or `-C target-cpu=cortex-m4`.
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use target::{Target, TargetOptions, TargetResult};
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pub fn target() -> TargetResult {

src/librustc_back/target/thumbv7em_none_eabihf.rs

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// option. This file may not be copied, modified, or distributed
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// except according to those terms.
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// Targets the Cortex-M4F and Cortex-M7F processors (ARMv7E-M)
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//
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// This target assumes that the device does have a FPU (Floating Point Unit) and lowers all (single
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// precision) floating point operations to hardware instructions.
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//
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// Additionally, this target uses the "hard" floating convention (ABI) where floating point values
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// are passed to/from subroutines via FPU registers (S0, S1, D0, D1, etc.).
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//
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// To opt into double precision hardware support, use the `-C target-feature=-fp-only-sp` flag.
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use target::{Target, TargetOptions, TargetResult};
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pub fn target() -> TargetResult {
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target_vendor: "".to_string(),
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options: TargetOptions {
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// vfp4 lowest common denominator between the Cortex-M4 (vfp4) and the Cortex-M7 (vfp5)
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features: "+vfp4".to_string(),
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// `+vfp4` is the lowest common denominator between the Cortex-M4 (vfp4-16) and the
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// Cortex-M7 (vfp5)
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// `+d16` both the Cortex-M4 and the Cortex-M7 only have 16 double-precision registers
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// available
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// `+fp-only-sp` The Cortex-M4 only supports single precision floating point operations
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// whereas in the Cortex-M7 double precision is optional
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features: "+vfp4,+d16,+fp-only-sp".to_string(),
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max_atomic_width: 32,
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.. super::thumb_base::opts()
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}

src/librustc_back/target/thumbv7m_none_eabi.rs

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// option. This file may not be copied, modified, or distributed
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// except according to those terms.
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// Targets the Cortex-M3 processor (ARMv7-M)
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use target::{Target, TargetOptions, TargetResult};
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pub fn target() -> TargetResult {

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