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bjorn3bjorn3
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Use Symbol for target features in asm handling
This saves a couple of Symbol::intern calls
1 parent a34c079 commit 991cbd1

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20 files changed

+91
-69
lines changed

20 files changed

+91
-69
lines changed

Diff for: ‎compiler/rustc_ast_lowering/src/asm.rs

+3-3
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ use rustc_data_structures::stable_set::FxHashSet;
66
use rustc_errors::struct_span_err;
77
use rustc_hir as hir;
88
use rustc_session::parse::feature_err;
9-
use rustc_span::{sym, Span, Symbol};
9+
use rustc_span::{sym, Span};
1010
use rustc_target::asm;
1111
use std::collections::hash_map::Entry;
1212
use std::fmt::Write;
@@ -66,7 +66,7 @@ impl<'a, 'hir> LoweringContext<'a, 'hir> {
6666
for (abi_name, abi_span) in &asm.clobber_abis {
6767
match asm::InlineAsmClobberAbi::parse(
6868
asm_arch,
69-
|feature| self.sess.target_features.contains(&Symbol::intern(feature)),
69+
|feature| self.sess.target_features.contains(&feature),
7070
&self.sess.target,
7171
*abi_name,
7272
) {
@@ -134,7 +134,7 @@ impl<'a, 'hir> LoweringContext<'a, 'hir> {
134134
asm::InlineAsmRegOrRegClass::Reg(if let Some(asm_arch) = asm_arch {
135135
asm::InlineAsmReg::parse(
136136
asm_arch,
137-
|feature| sess.target_features.contains(&Symbol::intern(feature)),
137+
|feature| sess.target_features.contains(&feature),
138138
&sess.target,
139139
s,
140140
)

Diff for: ‎compiler/rustc_codegen_cranelift/src/inline_asm.rs

+4-4
Original file line numberDiff line numberDiff line change
@@ -6,7 +6,7 @@ use std::fmt::Write;
66

77
use rustc_ast::ast::{InlineAsmOptions, InlineAsmTemplatePiece};
88
use rustc_middle::mir::InlineAsmOperand;
9-
use rustc_span::Symbol;
9+
use rustc_span::sym;
1010
use rustc_target::asm::*;
1111

1212
pub(crate) fn codegen_inline_asm<'tcx>(
@@ -184,7 +184,7 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
184184
let sess = self.tcx.sess;
185185
let map = allocatable_registers(
186186
self.arch,
187-
|feature| sess.target_features.contains(&Symbol::intern(feature)),
187+
|feature| sess.target_features.contains(&feature),
188188
&sess.target,
189189
);
190190
let mut allocated = FxHashMap::<_, (bool, bool)>::default();
@@ -319,9 +319,9 @@ impl<'tcx> InlineAssemblyGenerator<'_, 'tcx> {
319319
// Allocate stack slots for saving clobbered registers
320320
let abi_clobber = InlineAsmClobberAbi::parse(
321321
self.arch,
322-
|feature| self.tcx.sess.target_features.contains(&Symbol::intern(feature)),
322+
|feature| self.tcx.sess.target_features.contains(&feature),
323323
&self.tcx.sess.target,
324-
Symbol::intern("C"),
324+
sym::C,
325325
)
326326
.unwrap()
327327
.clobbered_regs();

Diff for: ‎compiler/rustc_codegen_gcc/src/asm.rs

+2-2
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,7 @@ use rustc_codegen_ssa::mir::place::PlaceRef;
55
use rustc_codegen_ssa::traits::{AsmBuilderMethods, AsmMethods, BaseTypeMethods, BuilderMethods, GlobalAsmOperandRef, InlineAsmOperandRef};
66

77
use rustc_middle::{bug, ty::Instance};
8-
use rustc_span::{Span, Symbol};
8+
use rustc_span::Span;
99
use rustc_target::asm::*;
1010

1111
use std::borrow::Cow;
@@ -172,7 +172,7 @@ impl<'a, 'gcc, 'tcx> AsmBuilderMethods<'tcx> for Builder<'a, 'gcc, 'tcx> {
172172
let is_target_supported = reg.reg_class().supported_types(asm_arch).iter()
173173
.any(|&(_, feature)| {
174174
if let Some(feature) = feature {
175-
self.tcx.sess.target_features.contains(&Symbol::intern(feature))
175+
self.tcx.sess.target_features.contains(&feature)
176176
} else {
177177
true // Register class is unconditionally supported
178178
}

Diff for: ‎compiler/rustc_codegen_llvm/src/asm.rs

+3-4
Original file line numberDiff line numberDiff line change
@@ -13,7 +13,7 @@ use rustc_codegen_ssa::traits::*;
1313
use rustc_data_structures::fx::FxHashMap;
1414
use rustc_middle::ty::layout::TyAndLayout;
1515
use rustc_middle::{bug, span_bug, ty::Instance};
16-
use rustc_span::{Pos, Span, Symbol};
16+
use rustc_span::{Pos, Span};
1717
use rustc_target::abi::*;
1818
use rustc_target::asm::*;
1919

@@ -45,9 +45,8 @@ impl<'ll, 'tcx> AsmBuilderMethods<'tcx> for Builder<'_, 'll, 'tcx> {
4545
for &(_, feature) in reg_class.supported_types(asm_arch) {
4646
if let Some(feature) = feature {
4747
let codegen_fn_attrs = self.tcx.codegen_fn_attrs(instance.def_id());
48-
let feature_name = Symbol::intern(feature);
49-
if self.tcx.sess.target_features.contains(&feature_name)
50-
|| codegen_fn_attrs.target_features.contains(&feature_name)
48+
if self.tcx.sess.target_features.contains(&feature)
49+
|| codegen_fn_attrs.target_features.contains(&feature)
5150
{
5251
return true;
5352
}

Diff for: ‎compiler/rustc_passes/src/intrinsicck.rs

+5-7
Original file line numberDiff line numberDiff line change
@@ -294,9 +294,8 @@ impl<'tcx> ExprVisitor<'tcx> {
294294
// (!). In that case we still need the earlier check to verify that the
295295
// register class is usable at all.
296296
if let Some(feature) = feature {
297-
let feat_sym = Symbol::intern(feature);
298-
if !self.tcx.sess.target_features.contains(&feat_sym)
299-
&& !target_features.contains(&feat_sym)
297+
if !self.tcx.sess.target_features.contains(&feature)
298+
&& !target_features.contains(&feature)
300299
{
301300
let msg = &format!("`{}` target feature is not enabled", feature);
302301
let mut err = self.tcx.sess.struct_span_err(expr.span, msg);
@@ -377,9 +376,8 @@ impl<'tcx> ExprVisitor<'tcx> {
377376
{
378377
match feature {
379378
Some(feature) => {
380-
let feat_sym = Symbol::intern(feature);
381-
if self.tcx.sess.target_features.contains(&feat_sym)
382-
|| attrs.target_features.contains(&feat_sym)
379+
if self.tcx.sess.target_features.contains(&feature)
380+
|| attrs.target_features.contains(&feature)
383381
{
384382
missing_required_features.clear();
385383
break;
@@ -413,7 +411,7 @@ impl<'tcx> ExprVisitor<'tcx> {
413411
let msg = format!(
414412
"register class `{}` requires at least one of the following target features: {}",
415413
reg_class.name(),
416-
features.join(", ")
414+
features.iter().map(|f| f.as_str()).collect::<Vec<_>>().join(", ")
417415
);
418416
self.tcx.sess.struct_span_err(*op_sp, &msg).emit();
419417
// register isn't enabled, don't do more checks

Diff for: ‎compiler/rustc_span/src/symbol.rs

+12
Original file line numberDiff line numberDiff line change
@@ -316,6 +316,7 @@ symbols! {
316316
allow_internal_unsafe,
317317
allow_internal_unstable,
318318
allowed,
319+
alu32,
319320
always,
320321
and,
321322
and_then,
@@ -361,7 +362,10 @@ symbols! {
361362
augmented_assignments,
362363
auto_traits,
363364
automatically_derived,
365+
avx,
364366
avx512_target_feature,
367+
avx512bw,
368+
avx512f,
365369
await_macro,
366370
bang,
367371
begin_panic,
@@ -592,6 +596,7 @@ symbols! {
592596
dylib,
593597
dyn_metadata,
594598
dyn_trait,
599+
e,
595600
edition_macro_pats,
596601
edition_panic,
597602
eh_catch_typeinfo,
@@ -682,6 +687,7 @@ symbols! {
682687
format_args_macro,
683688
format_args_nl,
684689
format_macro,
690+
fp,
685691
freeze,
686692
freg,
687693
frem_fast,
@@ -907,6 +913,7 @@ symbols! {
907913
neg,
908914
negate_unsigned,
909915
negative_impls,
916+
neon,
910917
never,
911918
never_type,
912919
never_type_fallback,
@@ -1101,6 +1108,7 @@ symbols! {
11011108
repr_packed,
11021109
repr_simd,
11031110
repr_transparent,
1111+
reserved_r9: "reserved-r9",
11041112
residual,
11051113
result,
11061114
rhs,
@@ -1294,6 +1302,7 @@ symbols! {
12941302
sqrtf64,
12951303
sreg,
12961304
sreg_low16,
1305+
sse,
12971306
sse4a_target_feature,
12981307
stable,
12991308
staged_api,
@@ -1360,6 +1369,8 @@ symbols! {
13601369
thread,
13611370
thread_local,
13621371
thread_local_macro,
1372+
thumb2,
1373+
thumb_mode: "thumb-mode",
13631374
todo_macro,
13641375
tool_attributes,
13651376
tool_lints,
@@ -1453,6 +1464,7 @@ symbols! {
14531464
vec,
14541465
vec_macro,
14551466
version,
1467+
vfp2,
14561468
vis,
14571469
visible_private_types,
14581470
volatile,

Diff for: ‎compiler/rustc_target/src/asm/aarch64.rs

+4-3
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
use super::{InlineAsmArch, InlineAsmType};
22
use crate::spec::Target;
33
use rustc_macros::HashStable_Generic;
4+
use rustc_span::Symbol;
45
use std::fmt;
56

67
def_reg_class! {
@@ -58,11 +59,11 @@ impl AArch64InlineAsmRegClass {
5859
pub fn supported_types(
5960
self,
6061
_arch: InlineAsmArch,
61-
) -> &'static [(InlineAsmType, Option<&'static str>)] {
62+
) -> &'static [(InlineAsmType, Option<Symbol>)] {
6263
match self {
6364
Self::reg => types! { _: I8, I16, I32, I64, F32, F64; },
6465
Self::vreg | Self::vreg_low16 => types! {
65-
"fp": I8, I16, I32, I64, F32, F64,
66+
fp: I8, I16, I32, I64, F32, F64,
6667
VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2), VecF64(1),
6768
VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4), VecF64(2);
6869
},
@@ -73,7 +74,7 @@ impl AArch64InlineAsmRegClass {
7374

7475
pub fn reserved_x18(
7576
_arch: InlineAsmArch,
76-
_has_feature: impl FnMut(&str) -> bool,
77+
_has_feature: impl FnMut(Symbol) -> bool,
7778
target: &Target,
7879
) -> Result<(), &'static str> {
7980
if target.os == "android"

Diff for: ‎compiler/rustc_target/src/asm/arm.rs

+13-12
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,7 @@
11
use super::{InlineAsmArch, InlineAsmType};
22
use crate::spec::Target;
33
use rustc_macros::HashStable_Generic;
4+
use rustc_span::{sym, Symbol};
45
use std::fmt;
56

67
def_reg_class! {
@@ -44,28 +45,28 @@ impl ArmInlineAsmRegClass {
4445
pub fn supported_types(
4546
self,
4647
_arch: InlineAsmArch,
47-
) -> &'static [(InlineAsmType, Option<&'static str>)] {
48+
) -> &'static [(InlineAsmType, Option<Symbol>)] {
4849
match self {
4950
Self::reg => types! { _: I8, I16, I32, F32; },
50-
Self::sreg | Self::sreg_low16 => types! { "vfp2": I32, F32; },
51+
Self::sreg | Self::sreg_low16 => types! { vfp2: I32, F32; },
5152
Self::dreg | Self::dreg_low16 | Self::dreg_low8 => types! {
52-
"vfp2": I64, F64, VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2);
53+
vfp2: I64, F64, VecI8(8), VecI16(4), VecI32(2), VecI64(1), VecF32(2);
5354
},
5455
Self::qreg | Self::qreg_low8 | Self::qreg_low4 => types! {
55-
"neon": VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4);
56+
neon: VecI8(16), VecI16(8), VecI32(4), VecI64(2), VecF32(4);
5657
},
5758
}
5859
}
5960
}
6061

6162
// This uses the same logic as useR7AsFramePointer in LLVM
62-
fn frame_pointer_is_r7(mut has_feature: impl FnMut(&str) -> bool, target: &Target) -> bool {
63-
target.is_like_osx || (!target.is_like_windows && has_feature("thumb-mode"))
63+
fn frame_pointer_is_r7(mut has_feature: impl FnMut(Symbol) -> bool, target: &Target) -> bool {
64+
target.is_like_osx || (!target.is_like_windows && has_feature(sym::thumb_mode))
6465
}
6566

6667
fn frame_pointer_r11(
6768
_arch: InlineAsmArch,
68-
has_feature: impl FnMut(&str) -> bool,
69+
has_feature: impl FnMut(Symbol) -> bool,
6970
target: &Target,
7071
) -> Result<(), &'static str> {
7172
if !frame_pointer_is_r7(has_feature, target) {
@@ -77,7 +78,7 @@ fn frame_pointer_r11(
7778

7879
fn frame_pointer_r7(
7980
_arch: InlineAsmArch,
80-
has_feature: impl FnMut(&str) -> bool,
81+
has_feature: impl FnMut(Symbol) -> bool,
8182
target: &Target,
8283
) -> Result<(), &'static str> {
8384
if frame_pointer_is_r7(has_feature, target) {
@@ -89,10 +90,10 @@ fn frame_pointer_r7(
8990

9091
fn not_thumb1(
9192
_arch: InlineAsmArch,
92-
mut has_feature: impl FnMut(&str) -> bool,
93+
mut has_feature: impl FnMut(Symbol) -> bool,
9394
_target: &Target,
9495
) -> Result<(), &'static str> {
95-
if has_feature("thumb-mode") && !has_feature("thumb2") {
96+
if has_feature(sym::thumb_mode) && !has_feature(sym::thumb2) {
9697
Err("high registers (r8+) cannot be used in Thumb-1 code")
9798
} else {
9899
Ok(())
@@ -101,14 +102,14 @@ fn not_thumb1(
101102

102103
fn reserved_r9(
103104
arch: InlineAsmArch,
104-
mut has_feature: impl FnMut(&str) -> bool,
105+
mut has_feature: impl FnMut(Symbol) -> bool,
105106
target: &Target,
106107
) -> Result<(), &'static str> {
107108
not_thumb1(arch, &mut has_feature, target)?;
108109

109110
// We detect this using the reserved-r9 feature instead of using the target
110111
// because the relocation model can be changed with compiler options.
111-
if has_feature("reserved-r9") {
112+
if has_feature(sym::reserved_r9) {
112113
Err("the RWPI static base register (r9) cannot be used as an operand for inline asm")
113114
} else {
114115
Ok(())

Diff for: ‎compiler/rustc_target/src/asm/avr.rs

+2-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
use super::{InlineAsmArch, InlineAsmType};
22
use rustc_macros::HashStable_Generic;
3+
use rustc_span::Symbol;
34
use std::fmt;
45

56
def_reg_class! {
@@ -39,7 +40,7 @@ impl AvrInlineAsmRegClass {
3940
pub fn supported_types(
4041
self,
4142
_arch: InlineAsmArch,
42-
) -> &'static [(InlineAsmType, Option<&'static str>)] {
43+
) -> &'static [(InlineAsmType, Option<Symbol>)] {
4344
match self {
4445
Self::reg => types! { _: I8; },
4546
Self::reg_upper => types! { _: I8; },

Diff for: ‎compiler/rustc_target/src/asm/bpf.rs

+5-4
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
use super::{InlineAsmArch, InlineAsmType, Target};
22
use rustc_macros::HashStable_Generic;
3+
use rustc_span::{sym, Symbol};
34
use std::fmt;
45

56
def_reg_class! {
@@ -33,20 +34,20 @@ impl BpfInlineAsmRegClass {
3334
pub fn supported_types(
3435
self,
3536
_arch: InlineAsmArch,
36-
) -> &'static [(InlineAsmType, Option<&'static str>)] {
37+
) -> &'static [(InlineAsmType, Option<Symbol>)] {
3738
match self {
3839
Self::reg => types! { _: I8, I16, I32, I64; },
39-
Self::wreg => types! { "alu32": I8, I16, I32; },
40+
Self::wreg => types! { alu32: I8, I16, I32; },
4041
}
4142
}
4243
}
4344

4445
fn only_alu32(
4546
_arch: InlineAsmArch,
46-
mut has_feature: impl FnMut(&str) -> bool,
47+
mut has_feature: impl FnMut(Symbol) -> bool,
4748
_target: &Target,
4849
) -> Result<(), &'static str> {
49-
if !has_feature("alu32") {
50+
if !has_feature(sym::alu32) {
5051
Err("register can't be used without the `alu32` target feature")
5152
} else {
5253
Ok(())

Diff for: ‎compiler/rustc_target/src/asm/hexagon.rs

+2-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
use super::{InlineAsmArch, InlineAsmType};
22
use rustc_macros::HashStable_Generic;
3+
use rustc_span::Symbol;
34
use std::fmt;
45

56
def_reg_class! {
@@ -32,7 +33,7 @@ impl HexagonInlineAsmRegClass {
3233
pub fn supported_types(
3334
self,
3435
_arch: InlineAsmArch,
35-
) -> &'static [(InlineAsmType, Option<&'static str>)] {
36+
) -> &'static [(InlineAsmType, Option<Symbol>)] {
3637
match self {
3738
Self::reg => types! { _: I8, I16, I32, F32; },
3839
}

Diff for: ‎compiler/rustc_target/src/asm/mips.rs

+2-1
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,6 @@
11
use super::{InlineAsmArch, InlineAsmType};
22
use rustc_macros::HashStable_Generic;
3+
use rustc_span::Symbol;
34
use std::fmt;
45

56
def_reg_class! {
@@ -33,7 +34,7 @@ impl MipsInlineAsmRegClass {
3334
pub fn supported_types(
3435
self,
3536
arch: InlineAsmArch,
36-
) -> &'static [(InlineAsmType, Option<&'static str>)] {
37+
) -> &'static [(InlineAsmType, Option<Symbol>)] {
3738
match (self, arch) {
3839
(Self::reg, InlineAsmArch::Mips64) => types! { _: I8, I16, I32, I64, F32, F64; },
3940
(Self::reg, _) => types! { _: I8, I16, I32, F32; },

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