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| 1 | +; RUN: llc -mtriple=riscv32 -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \ |
| 2 | +; RUN: grep -v "Verify generated machine code" | \ |
| 3 | +; RUN: FileCheck %s --check-prefixes=CHECK |
| 4 | +; RUN: llc -mtriple=riscv64 -O3 -debug-pass=Structure < %s -o /dev/null 2>&1 | \ |
| 5 | +; RUN: grep -v "Verify generated machine code" | \ |
| 6 | +; RUN: FileCheck %s --check-prefixes=CHECK,RV64 |
| 7 | + |
| 8 | +; REQUIRES: asserts |
| 9 | + |
| 10 | +; CHECK-LABEL: Pass Arguments: |
| 11 | +; CHECK-NEXT: Target Library Information |
| 12 | +; CHECK-NEXT: Target Pass Configuration |
| 13 | +; CHECK-NEXT: Machine Module Information |
| 14 | +; CHECK-NEXT: Target Transform Information |
| 15 | +; CHECK-NEXT: Type-Based Alias Analysis |
| 16 | +; CHECK-NEXT: Scoped NoAlias Alias Analysis |
| 17 | +; CHECK-NEXT: Assumption Cache Tracker |
| 18 | +; CHECK-NEXT: Profile summary info |
| 19 | +; CHECK-NEXT: Create Garbage Collector Module Metadata |
| 20 | +; CHECK-NEXT: Machine Branch Probability Analysis |
| 21 | +; CHECK-NEXT: Default Regalloc Eviction Advisor |
| 22 | +; CHECK-NEXT: ModulePass Manager |
| 23 | +; CHECK-NEXT: Pre-ISel Intrinsic Lowering |
| 24 | +; CHECK-NEXT: FunctionPass Manager |
| 25 | +; CHECK-NEXT: Expand Atomic instructions |
| 26 | +; CHECK-NEXT: Dominator Tree Construction |
| 27 | +; CHECK-NEXT: Natural Loop Information |
| 28 | +; CHECK-NEXT: RISCV gather/scatter lowering |
| 29 | +; CHECK-NEXT: Module Verifier |
| 30 | +; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) |
| 31 | +; CHECK-NEXT: Canonicalize natural loops |
| 32 | +; CHECK-NEXT: Scalar Evolution Analysis |
| 33 | +; CHECK-NEXT: Loop Pass Manager |
| 34 | +; CHECK-NEXT: Canonicalize Freeze Instructions in Loops |
| 35 | +; CHECK-NEXT: Induction Variable Users |
| 36 | +; CHECK-NEXT: Loop Strength Reduction |
| 37 | +; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) |
| 38 | +; CHECK-NEXT: Function Alias Analysis Results |
| 39 | +; CHECK-NEXT: Merge contiguous icmps into a memcmp |
| 40 | +; CHECK-NEXT: Natural Loop Information |
| 41 | +; CHECK-NEXT: Lazy Branch Probability Analysis |
| 42 | +; CHECK-NEXT: Lazy Block Frequency Analysis |
| 43 | +; CHECK-NEXT: Expand memcmp() to load/stores |
| 44 | +; CHECK-NEXT: Lower Garbage Collection Instructions |
| 45 | +; CHECK-NEXT: Shadow Stack GC Lowering |
| 46 | +; CHECK-NEXT: Lower constant intrinsics |
| 47 | +; CHECK-NEXT: Remove unreachable blocks from the CFG |
| 48 | +; CHECK-NEXT: Natural Loop Information |
| 49 | +; CHECK-NEXT: Post-Dominator Tree Construction |
| 50 | +; CHECK-NEXT: Branch Probability Analysis |
| 51 | +; CHECK-NEXT: Block Frequency Analysis |
| 52 | +; CHECK-NEXT: Constant Hoisting |
| 53 | +; CHECK-NEXT: Replace intrinsics with calls to vector library |
| 54 | +; CHECK-NEXT: Partially inline calls to library functions |
| 55 | +; CHECK-NEXT: Expand vector predication intrinsics |
| 56 | +; CHECK-NEXT: Scalarize Masked Memory Intrinsics |
| 57 | +; CHECK-NEXT: Expand reduction intrinsics |
| 58 | +; CHECK-NEXT: Natural Loop Information |
| 59 | +; CHECK-NEXT: TLS Variable Hoist |
| 60 | +; CHECK-NEXT: CodeGen Prepare |
| 61 | +; CHECK-NEXT: Dominator Tree Construction |
| 62 | +; CHECK-NEXT: Exception handling preparation |
| 63 | +; CHECK-NEXT: Safe Stack instrumentation pass |
| 64 | +; CHECK-NEXT: Insert stack protectors |
| 65 | +; CHECK-NEXT: Module Verifier |
| 66 | +; CHECK-NEXT: Basic Alias Analysis (stateless AA impl) |
| 67 | +; CHECK-NEXT: Function Alias Analysis Results |
| 68 | +; CHECK-NEXT: Natural Loop Information |
| 69 | +; CHECK-NEXT: Post-Dominator Tree Construction |
| 70 | +; CHECK-NEXT: Branch Probability Analysis |
| 71 | +; CHECK-NEXT: Lazy Branch Probability Analysis |
| 72 | +; CHECK-NEXT: Lazy Block Frequency Analysis |
| 73 | +; CHECK-NEXT: RISCV DAG->DAG Pattern Instruction Selection |
| 74 | +; CHECK-NEXT: Finalize ISel and expand pseudo-instructions |
| 75 | +; CHECK-NEXT: Lazy Machine Block Frequency Analysis |
| 76 | +; CHECK-NEXT: Early Tail Duplication |
| 77 | +; CHECK-NEXT: Optimize machine instruction PHIs |
| 78 | +; CHECK-NEXT: Slot index numbering |
| 79 | +; CHECK-NEXT: Merge disjoint stack slots |
| 80 | +; CHECK-NEXT: Local Stack Slot Allocation |
| 81 | +; CHECK-NEXT: Remove dead machine instructions |
| 82 | +; CHECK-NEXT: MachineDominator Tree Construction |
| 83 | +; CHECK-NEXT: Machine Natural Loop Construction |
| 84 | +; CHECK-NEXT: Machine Block Frequency Analysis |
| 85 | +; CHECK-NEXT: Early Machine Loop Invariant Code Motion |
| 86 | +; CHECK-NEXT: MachineDominator Tree Construction |
| 87 | +; CHECK-NEXT: Machine Block Frequency Analysis |
| 88 | +; CHECK-NEXT: Machine Common Subexpression Elimination |
| 89 | +; CHECK-NEXT: MachinePostDominator Tree Construction |
| 90 | +; CHECK-NEXT: Machine code sinking |
| 91 | +; CHECK-NEXT: Peephole Optimizations |
| 92 | +; CHECK-NEXT: Remove dead machine instructions |
| 93 | +; RV64-NEXT: RISCV sext.w Removal |
| 94 | +; CHECK-NEXT: RISCV Merge Base Offset |
| 95 | +; CHECK-NEXT: RISCV Insert VSETVLI pass |
| 96 | +; CHECK-NEXT: Detect Dead Lanes |
| 97 | +; CHECK-NEXT: Process Implicit Definitions |
| 98 | +; CHECK-NEXT: Remove unreachable machine basic blocks |
| 99 | +; CHECK-NEXT: Live Variable Analysis |
| 100 | +; CHECK-NEXT: Eliminate PHI nodes for register allocation |
| 101 | +; CHECK-NEXT: Two-Address instruction pass |
| 102 | +; CHECK-NEXT: MachineDominator Tree Construction |
| 103 | +; CHECK-NEXT: Slot index numbering |
| 104 | +; CHECK-NEXT: Live Interval Analysis |
| 105 | +; CHECK-NEXT: Simple Register Coalescing |
| 106 | +; CHECK-NEXT: Rename Disconnected Subregister Components |
| 107 | +; CHECK-NEXT: Machine Instruction Scheduler |
| 108 | +; CHECK-NEXT: Machine Block Frequency Analysis |
| 109 | +; CHECK-NEXT: Debug Variable Analysis |
| 110 | +; CHECK-NEXT: Live Stack Slot Analysis |
| 111 | +; CHECK-NEXT: Virtual Register Map |
| 112 | +; CHECK-NEXT: Live Register Matrix |
| 113 | +; CHECK-NEXT: Bundle Machine CFG Edges |
| 114 | +; CHECK-NEXT: Spill Code Placement Analysis |
| 115 | +; CHECK-NEXT: Lazy Machine Block Frequency Analysis |
| 116 | +; CHECK-NEXT: Machine Optimization Remark Emitter |
| 117 | +; CHECK-NEXT: Greedy Register Allocator |
| 118 | +; CHECK-NEXT: Virtual Register Rewriter |
| 119 | +; CHECK-NEXT: Register Allocation Pass Scoring |
| 120 | +; CHECK-NEXT: Stack Slot Coloring |
| 121 | +; CHECK-NEXT: Machine Copy Propagation Pass |
| 122 | +; CHECK-NEXT: Machine Loop Invariant Code Motion |
| 123 | +; CHECK-NEXT: RISCV Redundant Copy Elimination |
| 124 | +; CHECK-NEXT: Remove Redundant DEBUG_VALUE analysis |
| 125 | +; CHECK-NEXT: Fixup Statepoint Caller Saved |
| 126 | +; CHECK-NEXT: PostRA Machine Sink |
| 127 | +; CHECK-NEXT: MachineDominator Tree Construction |
| 128 | +; CHECK-NEXT: Machine Natural Loop Construction |
| 129 | +; CHECK-NEXT: Machine Block Frequency Analysis |
| 130 | +; CHECK-NEXT: MachinePostDominator Tree Construction |
| 131 | +; CHECK-NEXT: Lazy Machine Block Frequency Analysis |
| 132 | +; CHECK-NEXT: Machine Optimization Remark Emitter |
| 133 | +; CHECK-NEXT: Shrink Wrapping analysis |
| 134 | +; CHECK-NEXT: Prologue/Epilogue Insertion & Frame Finalization |
| 135 | +; CHECK-NEXT: Control Flow Optimizer |
| 136 | +; CHECK-NEXT: Lazy Machine Block Frequency Analysis |
| 137 | +; CHECK-NEXT: Tail Duplication |
| 138 | +; CHECK-NEXT: Machine Copy Propagation Pass |
| 139 | +; CHECK-NEXT: Post-RA pseudo instruction expansion pass |
| 140 | +; CHECK-NEXT: MachineDominator Tree Construction |
| 141 | +; CHECK-NEXT: Machine Natural Loop Construction |
| 142 | +; CHECK-NEXT: Post RA top-down list latency scheduler |
| 143 | +; CHECK-NEXT: Analyze Machine Code For Garbage Collection |
| 144 | +; CHECK-NEXT: Machine Block Frequency Analysis |
| 145 | +; CHECK-NEXT: MachinePostDominator Tree Construction |
| 146 | +; CHECK-NEXT: Branch Probability Basic Block Placement |
| 147 | +; CHECK-NEXT: Insert fentry calls |
| 148 | +; CHECK-NEXT: Insert XRay ops |
| 149 | +; CHECK-NEXT: Implement the 'patchable-function' attribute |
| 150 | +; CHECK-NEXT: Branch relaxation pass |
| 151 | +; CHECK-NEXT: Contiguously Lay Out Funclets |
| 152 | +; CHECK-NEXT: StackMap Liveness Analysis |
| 153 | +; CHECK-NEXT: Live DEBUG_VALUE analysis |
| 154 | +; CHECK-NEXT: RISCV pseudo instruction expansion pass |
| 155 | +; CHECK-NEXT: RISCV atomic pseudo instruction expansion pass |
| 156 | +; CHECK-NEXT: Lazy Machine Block Frequency Analysis |
| 157 | +; CHECK-NEXT: Machine Optimization Remark Emitter |
| 158 | +; CHECK-NEXT: RISCV Assembly Printer |
| 159 | +; CHECK-NEXT: Free MachineFunction |
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