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tesujitesuji
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Add asm! support for mips64
1 parent 6cb062d commit 79f477b

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5 files changed

+118
-82
lines changed

5 files changed

+118
-82
lines changed

‎compiler/rustc_codegen_llvm/src/asm.rs

+4-1
Original file line numberDiff line numberDiff line change
@@ -259,7 +259,7 @@ impl AsmBuilderMethods<'tcx> for Builder<'a, 'll, 'tcx> {
259259
InlineAsmArch::RiscV32 | InlineAsmArch::RiscV64 => {}
260260
InlineAsmArch::Nvptx64 => {}
261261
InlineAsmArch::Hexagon => {}
262-
InlineAsmArch::Mips => {}
262+
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {}
263263
}
264264
}
265265
if !options.contains(InlineAsmOptions::NOMEM) {
@@ -710,6 +710,7 @@ fn llvm_fixup_input(
710710
// MIPS only supports register-length arithmetics.
711711
Primitive::Int(Integer::I8 | Integer::I16, _) => bx.zext(value, bx.cx.type_i32()),
712712
Primitive::F32 => bx.bitcast(value, bx.cx.type_i32()),
713+
Primitive::F64 => bx.bitcast(value, bx.cx.type_i64()),
713714
_ => value,
714715
},
715716
_ => value,
@@ -785,6 +786,7 @@ fn llvm_fixup_output(
785786
Primitive::Int(Integer::I8, _) => bx.trunc(value, bx.cx.type_i8()),
786787
Primitive::Int(Integer::I16, _) => bx.trunc(value, bx.cx.type_i16()),
787788
Primitive::F32 => bx.bitcast(value, bx.cx.type_f32()),
789+
Primitive::F64 => bx.bitcast(value, bx.cx.type_f64()),
788790
_ => value,
789791
},
790792
_ => value,
@@ -854,6 +856,7 @@ fn llvm_fixup_output_type(
854856
// MIPS only supports register-length arithmetics.
855857
Primitive::Int(Integer::I8 | Integer::I16, _) => cx.type_i32(),
856858
Primitive::F32 => cx.type_i32(),
859+
Primitive::F64 => cx.type_i64(),
857860
_ => layout.llvm_type(cx),
858861
},
859862
_ => layout.llvm_type(cx),

‎compiler/rustc_target/src/asm/mips.rs

+5-4
Original file line numberDiff line numberDiff line change
@@ -32,11 +32,12 @@ impl MipsInlineAsmRegClass {
3232

3333
pub fn supported_types(
3434
self,
35-
_arch: InlineAsmArch,
35+
arch: InlineAsmArch,
3636
) -> &'static [(InlineAsmType, Option<&'static str>)] {
37-
match self {
38-
Self::reg => types! { _: I8, I16, I32, F32; },
39-
Self::freg => types! { _: F32, F64; },
37+
match (self, arch) {
38+
(Self::reg, InlineAsmArch::Mips64) => types! { _: I8, I16, I32, I64, F32, F64; },
39+
(Self::reg, _) => types! { _: I8, I16, I32, F32; },
40+
(Self::freg, _) => types! { _: F32, F64; },
4041
}
4142
}
4243
}

‎compiler/rustc_target/src/asm/mod.rs

+7-3
Original file line numberDiff line numberDiff line change
@@ -176,6 +176,7 @@ pub enum InlineAsmArch {
176176
Nvptx64,
177177
Hexagon,
178178
Mips,
179+
Mips64,
179180
}
180181

181182
impl FromStr for InlineAsmArch {
@@ -192,6 +193,7 @@ impl FromStr for InlineAsmArch {
192193
"nvptx64" => Ok(Self::Nvptx64),
193194
"hexagon" => Ok(Self::Hexagon),
194195
"mips" => Ok(Self::Mips),
196+
"mips64" => Ok(Self::Mips64),
195197
_ => Err(()),
196198
}
197199
}
@@ -259,7 +261,7 @@ impl InlineAsmReg {
259261
InlineAsmArch::Hexagon => {
260262
Self::Hexagon(HexagonInlineAsmReg::parse(arch, has_feature, target, &name)?)
261263
}
262-
InlineAsmArch::Mips => {
264+
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
263265
Self::Mips(MipsInlineAsmReg::parse(arch, has_feature, target, &name)?)
264266
}
265267
})
@@ -409,7 +411,9 @@ impl InlineAsmRegClass {
409411
InlineAsmArch::Hexagon => {
410412
Self::Hexagon(HexagonInlineAsmRegClass::parse(arch, name)?)
411413
}
412-
InlineAsmArch::Mips => Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?),
414+
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
415+
Self::Mips(MipsInlineAsmRegClass::parse(arch, name)?)
416+
}
413417
})
414418
})
415419
}
@@ -565,7 +569,7 @@ pub fn allocatable_registers(
565569
hexagon::fill_reg_map(arch, has_feature, target, &mut map);
566570
map
567571
}
568-
InlineAsmArch::Mips => {
572+
InlineAsmArch::Mips | InlineAsmArch::Mips64 => {
569573
let mut map = mips::regclass_map();
570574
mips::fill_reg_map(arch, has_feature, target, &mut map);
571575
map

‎src/doc/unstable-book/src/library-features/asm.md

+12-10
Original file line numberDiff line numberDiff line change
@@ -27,7 +27,7 @@ Inline assembly is currently supported on the following architectures:
2727
- RISC-V
2828
- NVPTX
2929
- Hexagon
30-
- MIPS32
30+
- MIPS32r2 and MIPS64r2
3131

3232
## Basic usage
3333

@@ -513,8 +513,8 @@ Here is the list of currently supported register classes:
513513
| ARM | `qreg` | `q[0-15]` | `w` |
514514
| ARM | `qreg_low8` | `q[0-7]` | `t` |
515515
| ARM | `qreg_low4` | `q[0-3]` | `x` |
516-
| MIPS32 | `reg` | `$[2-25]` | `r` |
517-
| MIPS32 | `freg` | `$f[0-31]` | `f` |
516+
| MIPS | `reg` | `$[2-25]` | `r` |
517+
| MIPS | `freg` | `$f[0-31]` | `f` |
518518
| NVPTX | `reg16` | None\* | `h` |
519519
| NVPTX | `reg32` | None\* | `r` |
520520
| NVPTX | `reg64` | None\* | `l` |
@@ -552,6 +552,8 @@ Each register class has constraints on which value types they can be used with.
552552
| ARM | `qreg` | `neon` | `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4` |
553553
| MIPS32 | `reg` | None | `i8`, `i16`, `i32`, `f32` |
554554
| MIPS32 | `freg` | None | `f32`, `f64` |
555+
| MIPS64 | `reg` | None | `i8`, `i16`, `i32`, `i64`, `f32`, `f64` |
556+
| MIPS64 | `freg` | None | `f32`, `f64` |
555557
| NVPTX | `reg16` | None | `i8`, `i16` |
556558
| NVPTX | `reg32` | None | `i8`, `i16`, `i32`, `f32` |
557559
| NVPTX | `reg64` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
@@ -637,11 +639,11 @@ Some registers cannot be used for input or output operands:
637639
| x86 | `st([0-7])` | x87 registers are not currently supported (but may be in the future). |
638640
| AArch64 | `xzr` | This is a constant zero register which can't be modified. |
639641
| ARM | `pc` | This is the program counter, not a real register. |
640-
| MIPS32 | `$0` or `$zero` | This is a constant zero register which can't be modified. |
641-
| MIPS32 | `$1` or `$at` | Reserved for assembler. |
642-
| MIPS32 | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. |
643-
| MIPS32 | `$28`/`$gp` | Global pointer cannot be used as inputs or outputs. |
644-
| MIPS32 | `$ra` | Return address cannot be used as inputs or outputs. |
642+
| MIPS | `$0` or `$zero` | This is a constant zero register which can't be modified. |
643+
| MIPS | `$1` or `$at` | Reserved for assembler. |
644+
| MIPS | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. |
645+
| MIPS | `$28`/`$gp` | Global pointer cannot be used as inputs or outputs. |
646+
| MIPS | `$ra` | Return address cannot be used as inputs or outputs. |
645647
| RISC-V | `x0` | This is a constant zero register which can't be modified. |
646648
| RISC-V | `gp`, `tp` | These registers are reserved and cannot be used as inputs or outputs. |
647649
| Hexagon | `lr` | This is the link register which cannot be used as an input or output. |
@@ -689,8 +691,8 @@ The supported modifiers are a subset of LLVM's (and GCC's) [asm template argumen
689691
| ARM | `dreg` | None | `d0` | `P` |
690692
| ARM | `qreg` | None | `q0` | `q` |
691693
| ARM | `qreg` | `e` / `f` | `d0` / `d1` | `e` / `f` |
692-
| MIPS32 | `reg` | None | `$2` | None |
693-
| MIPS32 | `freg` | None | `$f0` | None |
694+
| MIPS | `reg` | None | `$2` | None |
695+
| MIPS | `freg` | None | `$f0` | None |
694696
| NVPTX | `reg16` | None | `rs0` | None |
695697
| NVPTX | `reg32` | None | `r0` | None |
696698
| NVPTX | `reg64` | None | `rd0` | None |

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