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1 parent 36f4f4a commit 52ef8cdCopy full SHA for 52ef8cd
compiler/rustc_mir_transform/src/inline.rs
@@ -47,9 +47,8 @@ impl<'tcx> MirPass<'tcx> for Inline {
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match sess.mir_opt_level() {
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0 | 1 => false,
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2 => {
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- (sess.opts.optimize == OptLevel::Default
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- || sess.opts.optimize == OptLevel::Aggressive)
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- && sess.opts.incremental == None
+ sess.opts.optimize == OptLevel::Default
+ || sess.opts.optimize == OptLevel::Aggressive
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}
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_ => true,
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