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bjorn3bjorn3
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Remove no longer used vendor intrinsic implementations
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‎src/intrinsics/llvm_x86.rs

-161
Original file line numberDiff line numberDiff line change
@@ -169,56 +169,6 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>(
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}
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}
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172-
"llvm.x86.sse.add.ss" => {
173-
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_add_ss&ig_expand=171
174-
intrinsic_args!(fx, args => (a, b); intrinsic);
175-
176-
assert_eq!(a.layout(), b.layout());
177-
assert_eq!(a.layout(), ret.layout());
178-
let layout = a.layout();
179-
180-
let (_, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
181-
assert!(lane_ty.is_floating_point());
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let ret_lane_layout = fx.layout_of(lane_ty);
183-
184-
ret.write_cvalue(fx, a);
185-
186-
let a_lane = a.value_lane(fx, 0).load_scalar(fx);
187-
let b_lane = b.value_lane(fx, 0).load_scalar(fx);
188-
189-
let res = fx.bcx.ins().fadd(a_lane, b_lane);
190-
191-
let res_lane = CValue::by_val(res, ret_lane_layout);
192-
ret.place_lane(fx, 0).write_cvalue(fx, res_lane);
193-
}
194-
195-
"llvm.x86.sse.sqrt.ss" => {
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// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sqrt_ss&ig_expand=6278
197-
intrinsic_args!(fx, args => (a); intrinsic);
198-
199-
assert_eq!(a.layout(), ret.layout());
200-
let (_, lane_ty) = a.layout().ty.simd_size_and_type(fx.tcx);
201-
assert!(lane_ty.is_floating_point());
202-
let ret_lane_layout = fx.layout_of(lane_ty);
203-
204-
ret.write_cvalue(fx, a);
205-
206-
let lane = a.value_lane(fx, 0).load_scalar(fx);
207-
let res = fx.bcx.ins().sqrt(lane);
208-
let res_lane = CValue::by_val(res, ret_lane_layout);
209-
ret.place_lane(fx, 0).write_cvalue(fx, res_lane);
210-
}
211-
212-
"llvm.x86.sse.sqrt.ps" => {
213-
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_sqrt_ps&ig_expand=6245
214-
intrinsic_args!(fx, args => (a); intrinsic);
215-
216-
// FIXME use vector instructions when possible
217-
simd_for_each_lane(fx, a, ret, &|fx, _lane_ty, _res_lane_ty, lane| {
218-
fx.bcx.ins().sqrt(lane)
219-
});
220-
}
221-
222172
"llvm.x86.sse.max.ps" => {
223173
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_max_ps&ig_expand=4357
224174
intrinsic_args!(fx, args => (a, b); intrinsic);
@@ -761,117 +711,6 @@ pub(crate) fn codegen_x86_llvm_intrinsic_call<'tcx>(
761711
pack_instruction(fx, a, b, ret, PackSize::S16, PackWidth::Avx);
762712
}
763713

764-
"llvm.x86.fma.vfmaddsub.ps"
765-
| "llvm.x86.fma.vfmaddsub.pd"
766-
| "llvm.x86.fma.vfmaddsub.ps.256"
767-
| "llvm.x86.fma.vfmaddsub.pd.256" => {
768-
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_fmaddsub_ps&ig_expand=3205
769-
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_fmaddsub_pd&ig_expand=3181
770-
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_fmaddsub_ps&ig_expand=3209
771-
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_fmaddsub_pd&ig_expand=3185
772-
intrinsic_args!(fx, args => (a, b, c); intrinsic);
773-
774-
assert_eq!(a.layout(), b.layout());
775-
assert_eq!(a.layout(), c.layout());
776-
let layout = a.layout();
777-
778-
let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
779-
let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
780-
assert!(lane_ty.is_floating_point());
781-
assert!(ret_lane_ty.is_floating_point());
782-
assert_eq!(lane_count, ret_lane_count);
783-
let ret_lane_layout = fx.layout_of(ret_lane_ty);
784-
785-
for idx in 0..lane_count {
786-
let a_lane = a.value_lane(fx, idx).load_scalar(fx);
787-
let b_lane = b.value_lane(fx, idx).load_scalar(fx);
788-
let c_lane = c.value_lane(fx, idx).load_scalar(fx);
789-
790-
let mul = fx.bcx.ins().fmul(a_lane, b_lane);
791-
let res = if idx & 1 == 0 {
792-
fx.bcx.ins().fsub(mul, c_lane)
793-
} else {
794-
fx.bcx.ins().fadd(mul, c_lane)
795-
};
796-
797-
let res_lane = CValue::by_val(res, ret_lane_layout);
798-
ret.place_lane(fx, idx).write_cvalue(fx, res_lane);
799-
}
800-
}
801-
802-
"llvm.x86.fma.vfmsubadd.ps"
803-
| "llvm.x86.fma.vfmsubadd.pd"
804-
| "llvm.x86.fma.vfmsubadd.ps.256"
805-
| "llvm.x86.fma.vfmsubadd.pd.256" => {
806-
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_fmsubadd_ps&ig_expand=3325
807-
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_fmsubadd_pd&ig_expand=3301
808-
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_fmsubadd_ps&ig_expand=3329
809-
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_fmsubadd_pd&ig_expand=3305
810-
intrinsic_args!(fx, args => (a, b, c); intrinsic);
811-
812-
assert_eq!(a.layout(), b.layout());
813-
assert_eq!(a.layout(), c.layout());
814-
let layout = a.layout();
815-
816-
let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
817-
let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
818-
assert!(lane_ty.is_floating_point());
819-
assert!(ret_lane_ty.is_floating_point());
820-
assert_eq!(lane_count, ret_lane_count);
821-
let ret_lane_layout = fx.layout_of(ret_lane_ty);
822-
823-
for idx in 0..lane_count {
824-
let a_lane = a.value_lane(fx, idx).load_scalar(fx);
825-
let b_lane = b.value_lane(fx, idx).load_scalar(fx);
826-
let c_lane = c.value_lane(fx, idx).load_scalar(fx);
827-
828-
let mul = fx.bcx.ins().fmul(a_lane, b_lane);
829-
let res = if idx & 1 == 0 {
830-
fx.bcx.ins().fadd(mul, c_lane)
831-
} else {
832-
fx.bcx.ins().fsub(mul, c_lane)
833-
};
834-
835-
let res_lane = CValue::by_val(res, ret_lane_layout);
836-
ret.place_lane(fx, idx).write_cvalue(fx, res_lane);
837-
}
838-
}
839-
840-
"llvm.x86.fma.vfnmadd.ps"
841-
| "llvm.x86.fma.vfnmadd.pd"
842-
| "llvm.x86.fma.vfnmadd.ps.256"
843-
| "llvm.x86.fma.vfnmadd.pd.256" => {
844-
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_fnmadd_ps&ig_expand=3391
845-
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm_fnmadd_pd&ig_expand=3367
846-
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_fnmadd_ps&ig_expand=3395
847-
// https://www.intel.com/content/www/us/en/docs/intrinsics-guide/index.html#text=_mm256_fnmadd_pd&ig_expand=3371
848-
intrinsic_args!(fx, args => (a, b, c); intrinsic);
849-
850-
assert_eq!(a.layout(), b.layout());
851-
assert_eq!(a.layout(), c.layout());
852-
let layout = a.layout();
853-
854-
let (lane_count, lane_ty) = layout.ty.simd_size_and_type(fx.tcx);
855-
let (ret_lane_count, ret_lane_ty) = ret.layout().ty.simd_size_and_type(fx.tcx);
856-
assert!(lane_ty.is_floating_point());
857-
assert!(ret_lane_ty.is_floating_point());
858-
assert_eq!(lane_count, ret_lane_count);
859-
let ret_lane_layout = fx.layout_of(ret_lane_ty);
860-
861-
for idx in 0..lane_count {
862-
let a_lane = a.value_lane(fx, idx).load_scalar(fx);
863-
let b_lane = b.value_lane(fx, idx).load_scalar(fx);
864-
let c_lane = c.value_lane(fx, idx).load_scalar(fx);
865-
866-
let mul = fx.bcx.ins().fmul(a_lane, b_lane);
867-
let neg_mul = fx.bcx.ins().fneg(mul);
868-
let res = fx.bcx.ins().fadd(neg_mul, c_lane);
869-
870-
let res_lane = CValue::by_val(res, ret_lane_layout);
871-
ret.place_lane(fx, idx).write_cvalue(fx, res_lane);
872-
}
873-
}
874-
875714
"llvm.x86.sse42.crc32.32.8"
876715
| "llvm.x86.sse42.crc32.32.16"
877716
| "llvm.x86.sse42.crc32.32.32"

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