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Commit 88bda2e

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jbhatejaalexcrichton
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[WebAssembly] Fix stack offsets of return values from call lowering.
Summary: Fixes PR35220 Reviewers: vadimcn, alexcrichton Reviewed By: alexcrichton Subscribers: pepyakin, alexcrichton, jfb, dschuff, sbc100, jgravelle-google, llvm-commits, aheejin Differential Revision: https://reviews.llvm.org/D39866 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@317895 91177308-0d34-0410-b5e6-96231b3b80d8
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-3
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2 files changed

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lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7667,10 +7667,10 @@ TargetLowering::LowerCallTo(TargetLowering::CallLoweringInfo &CLI) const {
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uint64_t Offset = OldOffsets[i];
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MVT RegisterVT = getRegisterType(CLI.RetTy->getContext(), RetVT);
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unsigned NumRegs = getNumRegisters(CLI.RetTy->getContext(), RetVT);
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unsigned RegisterVTSize = RegisterVT.getSizeInBits();
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unsigned RegisterVTByteSZ = RegisterVT.getSizeInBits() / 8;
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RetTys.append(NumRegs, RegisterVT);
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for (unsigned j = 0; j != NumRegs; ++j)
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Offsets.push_back(Offset + j * RegisterVTSize);
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Offsets.push_back(Offset + j * RegisterVTByteSZ);
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}
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}
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test/CodeGen/WebAssembly/umulo-i64.ll

Lines changed: 12 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,7 +1,7 @@
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; RUN: llc < %s -asm-verbose=false | FileCheck %s
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; Test that UMULO works correctly on 64-bit operands.
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
4-
target triple = "wasm32-unknown-emscripten"
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target triple = "wasm32-unknown-unknown"
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; CHECK-LABEL: _ZN4core3num21_$LT$impl$u20$u64$GT$15overflowing_mul17h07be88b4cbac028fE:
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; CHECK: __multi3
@@ -19,3 +19,14 @@ declare { i64, i1 } @llvm.umul.with.overflow.i64(i64, i64) #1
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attributes #0 = { inlinehint }
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attributes #1 = { nounwind readnone speculatable }
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; CHECK-LABEL: wut:
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; CHECK: call __multi3@FUNCTION, $2, $0, $pop0, $1, $pop10
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; CHECK: i64.load $0=, 8($2)
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define i1 @wut(i64, i64) {
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start:
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%2 = call { i64, i1 } @llvm.umul.with.overflow.i64(i64 %0, i64 %1)
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%3 = extractvalue { i64, i1 } %2, 1
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ret i1 %3
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}
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