Skip to content
This repository was archived by the owner on Feb 5, 2019. It is now read-only.

Commit 5cc14a0

Browse files
pirama-arumuga-nainararielb1
authored andcommitted
Fix computeKnownBits for ARMISD::CMOV
Summary: The true and false operands for the CMOV are operands 0 and 1. ARMISelLowering.cpp::computeKnownBits was looking at operands 1 and 2 instead. This can cause CMOV instructions to be incorrectly folded into BFI if value set by the CMOV is another CMOV, whose known bits are computed incorrectly. This patch fixes the issue and adds a test case. Reviewers: kristof.beyls, jmolloy Subscribers: llvm-commits, aemerson, srhines, rengolin Differential Revision: https://reviews.llvm.org/D31265 git-svn-id: https://llvm.org/svn/llvm-project/llvm/trunk@298624 91177308-0d34-0410-b5e6-96231b3b80d8
1 parent c782feb commit 5cc14a0

File tree

2 files changed

+21
-2
lines changed

2 files changed

+21
-2
lines changed

lib/Target/ARM/ARMISelLowering.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -11324,8 +11324,8 @@ static void computeKnownBits(SelectionDAG &DAG, SDValue Op, APInt &KnownZero,
1132411324
if (Op.getOpcode() == ARMISD::CMOV) {
1132511325
APInt KZ2(KnownZero.getBitWidth(), 0);
1132611326
APInt KO2(KnownOne.getBitWidth(), 0);
11327-
computeKnownBits(DAG, Op.getOperand(1), KnownZero, KnownOne);
11328-
computeKnownBits(DAG, Op.getOperand(2), KZ2, KO2);
11327+
computeKnownBits(DAG, Op.getOperand(0), KnownZero, KnownOne);
11328+
computeKnownBits(DAG, Op.getOperand(1), KZ2, KO2);
1132911329

1133011330
KnownZero &= KZ2;
1133111331
KnownOne &= KO2;

test/CodeGen/ARM/no-cmov2bfi.ll

+19
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,19 @@
1+
; RUN: llc < %s -mtriple=thumbv7 | FileCheck --check-prefix=CHECK-NOBFI %s
2+
3+
declare zeroext i1 @dummy()
4+
5+
define i8 @test(i8 %a1, i1 %c) {
6+
; CHECK-NOBFI-NOT: bfi
7+
; CHECK-NOBFI: bl dummy
8+
; CHECK-NOBFI: cmp r0, #0
9+
; CHECK-NOBFI: it ne
10+
; CHECK-NOBFI: orrne [[REG:r[0-9]+]], [[REG]], #8
11+
; CHECK-NOBFI: mov r0, [[REG]]
12+
13+
%1 = and i8 %a1, -9
14+
%2 = select i1 %c, i8 %1, i8 %a1
15+
%3 = tail call zeroext i1 @dummy()
16+
%4 = or i8 %2, 8
17+
%ret = select i1 %3, i8 %4, i8 %2
18+
ret i8 %ret
19+
}

0 commit comments

Comments
 (0)