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[WebAssembly] Update v128.any_true
In the final SIMD spec, there is only a single v128.any_true instruction, rather than one for each lane interpretation because the semantics do not depend on the lane interpretation. Differential Revision: https://reviews.llvm.org/D100241
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‎llvm/lib/Target/WebAssembly/WebAssemblyInstrSIMD.td

Lines changed: 29 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -822,22 +822,44 @@ defm ABS : SIMDUnaryInt<abs, "abs", 96>;
822822
// Integer negation: neg
823823
defm NEG : SIMDUnaryInt<ivneg, "neg", 97>;
824824

825+
// Population count: popcnt
826+
defm POPCNT : SIMDUnary<I8x16, int_wasm_popcnt, "popcnt", 0x62>;
827+
825828
// Any lane true: any_true
826-
defm ANYTRUE : SIMDReduce<int_wasm_anytrue, "any_true", 98>;
829+
defm ANYTRUE : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins), [],
830+
"v128.any_true\t$dst, $vec", "v128.any_true", 0x53>;
831+
832+
foreach vec = IntVecs in
833+
def : Pat<(int_wasm_anytrue (vec.vt V128:$vec)), (ANYTRUE V128:$vec)>;
827834

828835
// All lanes true: all_true
829-
defm ALLTRUE : SIMDReduce<int_wasm_alltrue, "all_true", 99>;
836+
multiclass SIMDAllTrue<Vec vec, bits<32> simdop> {
837+
defm ALLTRUE_#vec : SIMD_I<(outs I32:$dst), (ins V128:$vec), (outs), (ins),
838+
[(set I32:$dst,
839+
(i32 (int_wasm_alltrue (vec.vt V128:$vec))))],
840+
vec.prefix#".all_true\t$dst, $vec",
841+
vec.prefix#".all_true", simdop>;
842+
}
830843

831-
// Population count: popcnt
832-
defm POPCNT : SIMDUnary<I8x16, int_wasm_popcnt, "popcnt", 0x62>;
844+
defm "" : SIMDAllTrue<I8x16, 0x63>;
845+
defm "" : SIMDAllTrue<I16x8, 0x83>;
846+
defm "" : SIMDAllTrue<I32x4, 0xa3>;
847+
defm "" : SIMDAllTrue<I64x2, 0xc3>;
833848

834849
// Reductions already return 0 or 1, so and 1, setne 0, and seteq 1
835850
// can be folded out
836851
foreach reduction =
837-
[["int_wasm_anytrue", "ANYTRUE"], ["int_wasm_alltrue", "ALLTRUE"]] in
838-
foreach vec = IntVecs in {
852+
[["int_wasm_anytrue", "ANYTRUE", "I8x16"],
853+
["int_wasm_anytrue", "ANYTRUE", "I16x8"],
854+
["int_wasm_anytrue", "ANYTRUE", "I32x4"],
855+
["int_wasm_anytrue", "ANYTRUE", "I64x2"],
856+
["int_wasm_alltrue", "ALLTRUE_I8x16", "I8x16"],
857+
["int_wasm_alltrue", "ALLTRUE_I16x8", "I16x8"],
858+
["int_wasm_alltrue", "ALLTRUE_I32x4", "I32x4"],
859+
["int_wasm_alltrue", "ALLTRUE_I64x2", "I64x2"]] in {
839860
defvar intrinsic = !cast<Intrinsic>(reduction[0]);
840-
defvar inst = !cast<NI>(reduction[1]#"_"#vec);
861+
defvar inst = !cast<NI>(reduction[1]);
862+
defvar vec = !cast<Vec>(reduction[2]);
841863
def : Pat<(i32 (and (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>;
842864
def : Pat<(i32 (setne (i32 (intrinsic (vec.vt V128:$x))), (i32 0))), (inst $x)>;
843865
def : Pat<(i32 (seteq (i32 (intrinsic (vec.vt V128:$x))), (i32 1))), (inst $x)>;

‎llvm/test/CodeGen/WebAssembly/simd-intrinsics.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -87,7 +87,7 @@ define <16 x i8> @popcnt_v16i8(<16 x i8> %x) {
8787

8888
; CHECK-LABEL: any_v16i8:
8989
; CHECK-NEXT: .functype any_v16i8 (v128) -> (i32){{$}}
90-
; CHECK-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
90+
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
9191
; CHECK-NEXT: return $pop[[R]]{{$}}
9292
declare i32 @llvm.wasm.anytrue.v16i8(<16 x i8>)
9393
define i32 @any_v16i8(<16 x i8> %x) {
@@ -319,7 +319,7 @@ define <8 x i16> @extadd_pairwise_u_v8i16(<16 x i8> %x) {
319319

320320
; CHECK-LABEL: any_v8i16:
321321
; CHECK-NEXT: .functype any_v8i16 (v128) -> (i32){{$}}
322-
; CHECK-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
322+
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
323323
; CHECK-NEXT: return $pop[[R]]{{$}}
324324
declare i32 @llvm.wasm.anytrue.v8i16(<8 x i16>)
325325
define i32 @any_v8i16(<8 x i16> %x) {
@@ -468,7 +468,7 @@ define <4 x i32> @extadd_pairwise_u_v4i32(<8 x i16> %x) {
468468

469469
; CHECK-LABEL: any_v4i32:
470470
; CHECK-NEXT: .functype any_v4i32 (v128) -> (i32){{$}}
471-
; CHECK-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
471+
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
472472
; CHECK-NEXT: return $pop[[R]]{{$}}
473473
declare i32 @llvm.wasm.anytrue.v4i32(<4 x i32>)
474474
define i32 @any_v4i32(<4 x i32> %x) {
@@ -643,7 +643,7 @@ define <2 x i64> @extmul_high_u_v2i64(<4 x i32> %x, <4 x i32> %y) {
643643

644644
; CHECK-LABEL: any_v2i64:
645645
; CHECK-NEXT: .functype any_v2i64 (v128) -> (i32){{$}}
646-
; CHECK-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
646+
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
647647
; CHECK-NEXT: return $pop[[R]]{{$}}
648648
declare i32 @llvm.wasm.anytrue.v2i64(<2 x i64>)
649649
define i32 @any_v2i64(<2 x i64> %x) {

‎llvm/test/CodeGen/WebAssembly/simd-reductions.ll

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,7 @@ declare i32 @llvm.wasm.alltrue.v16i8(<16 x i8>)
1414

1515
; CHECK-LABEL: any_v16i8_trunc:
1616
; CHECK-NEXT: .functype any_v16i8_trunc (v128) -> (i32){{$}}
17-
; CHECK-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
17+
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
1818
; CHECK-NEXT: return $pop[[R]]{{$}}
1919
define i32 @any_v16i8_trunc(<16 x i8> %x) {
2020
%a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
@@ -25,7 +25,7 @@ define i32 @any_v16i8_trunc(<16 x i8> %x) {
2525

2626
; CHECK-LABEL: any_v16i8_ne:
2727
; CHECK-NEXT: .functype any_v16i8_ne (v128) -> (i32){{$}}
28-
; CHECK-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
28+
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
2929
; CHECK-NEXT: return $pop[[R]]{{$}}
3030
define i32 @any_v16i8_ne(<16 x i8> %x) {
3131
%a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
@@ -36,7 +36,7 @@ define i32 @any_v16i8_ne(<16 x i8> %x) {
3636

3737
; CHECK-LABEL: any_v16i8_eq:
3838
; CHECK-NEXT: .functype any_v16i8_eq (v128) -> (i32){{$}}
39-
; CHECK-NEXT: i8x16.any_true $push[[R:[0-9]+]]=, $0{{$}}
39+
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
4040
; CHECK-NEXT: return $pop[[R]]{{$}}
4141
define i32 @any_v16i8_eq(<16 x i8> %x) {
4242
%a = call i32 @llvm.wasm.anytrue.v16i8(<16 x i8> %x)
@@ -86,7 +86,7 @@ declare i32 @llvm.wasm.alltrue.v8i16(<8 x i16>)
8686

8787
; CHECK-LABEL: any_v8i16_trunc:
8888
; CHECK-NEXT: .functype any_v8i16_trunc (v128) -> (i32){{$}}
89-
; CHECK-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
89+
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
9090
; CHECK-NEXT: return $pop[[R]]{{$}}
9191
define i32 @any_v8i16_trunc(<8 x i16> %x) {
9292
%a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
@@ -97,7 +97,7 @@ define i32 @any_v8i16_trunc(<8 x i16> %x) {
9797

9898
; CHECK-LABEL: any_v8i16_ne:
9999
; CHECK-NEXT: .functype any_v8i16_ne (v128) -> (i32){{$}}
100-
; CHECK-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
100+
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
101101
; CHECK-NEXT: return $pop[[R]]{{$}}
102102
define i32 @any_v8i16_ne(<8 x i16> %x) {
103103
%a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
@@ -108,7 +108,7 @@ define i32 @any_v8i16_ne(<8 x i16> %x) {
108108

109109
; CHECK-LABEL: any_v8i16_eq:
110110
; CHECK-NEXT: .functype any_v8i16_eq (v128) -> (i32){{$}}
111-
; CHECK-NEXT: i16x8.any_true $push[[R:[0-9]+]]=, $0{{$}}
111+
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
112112
; CHECK-NEXT: return $pop[[R]]{{$}}
113113
define i32 @any_v8i16_eq(<8 x i16> %x) {
114114
%a = call i32 @llvm.wasm.anytrue.v8i16(<8 x i16> %x)
@@ -158,7 +158,7 @@ declare i32 @llvm.wasm.alltrue.v4i32(<4 x i32>)
158158

159159
; CHECK-LABEL: any_v4i32_trunc:
160160
; CHECK-NEXT: .functype any_v4i32_trunc (v128) -> (i32){{$}}
161-
; CHECK-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
161+
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
162162
; CHECK-NEXT: return $pop[[R]]{{$}}
163163
define i32 @any_v4i32_trunc(<4 x i32> %x) {
164164
%a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
@@ -169,7 +169,7 @@ define i32 @any_v4i32_trunc(<4 x i32> %x) {
169169

170170
; CHECK-LABEL: any_v4i32_ne:
171171
; CHECK-NEXT: .functype any_v4i32_ne (v128) -> (i32){{$}}
172-
; CHECK-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
172+
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
173173
; CHECK-NEXT: return $pop[[R]]{{$}}
174174
define i32 @any_v4i32_ne(<4 x i32> %x) {
175175
%a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
@@ -180,7 +180,7 @@ define i32 @any_v4i32_ne(<4 x i32> %x) {
180180

181181
; CHECK-LABEL: any_v4i32_eq:
182182
; CHECK-NEXT: .functype any_v4i32_eq (v128) -> (i32){{$}}
183-
; CHECK-NEXT: i32x4.any_true $push[[R:[0-9]+]]=, $0{{$}}
183+
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
184184
; CHECK-NEXT: return $pop[[R]]{{$}}
185185
define i32 @any_v4i32_eq(<4 x i32> %x) {
186186
%a = call i32 @llvm.wasm.anytrue.v4i32(<4 x i32> %x)
@@ -230,7 +230,7 @@ declare i32 @llvm.wasm.alltrue.v2i64(<2 x i64>)
230230

231231
; CHECK-LABEL: any_v2i64_trunc:
232232
; CHECK-NEXT: .functype any_v2i64_trunc (v128) -> (i32){{$}}
233-
; CHECK-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
233+
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
234234
; CHECK-NEXT: return $pop[[R]]{{$}}
235235
define i32 @any_v2i64_trunc(<2 x i64> %x) {
236236
%a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
@@ -241,7 +241,7 @@ define i32 @any_v2i64_trunc(<2 x i64> %x) {
241241

242242
; CHECK-LABEL: any_v2i64_ne:
243243
; CHECK-NEXT: .functype any_v2i64_ne (v128) -> (i32){{$}}
244-
; CHECK-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
244+
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
245245
; CHECK-NEXT: return $pop[[R]]{{$}}
246246
define i32 @any_v2i64_ne(<2 x i64> %x) {
247247
%a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)
@@ -252,7 +252,7 @@ define i32 @any_v2i64_ne(<2 x i64> %x) {
252252

253253
; CHECK-LABEL: any_v2i64_eq:
254254
; CHECK-NEXT: .functype any_v2i64_eq (v128) -> (i32){{$}}
255-
; CHECK-NEXT: i64x2.any_true $push[[R:[0-9]+]]=, $0{{$}}
255+
; CHECK-NEXT: v128.any_true $push[[R:[0-9]+]]=, $0{{$}}
256256
; CHECK-NEXT: return $pop[[R]]{{$}}
257257
define i32 @any_v2i64_eq(<2 x i64> %x) {
258258
%a = call i32 @llvm.wasm.anytrue.v2i64(<2 x i64> %x)

‎llvm/test/MC/Disassembler/WebAssembly/wasm.txt

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -43,8 +43,7 @@
4343
0xFD 0x83 0x01
4444

4545
# Including non-canonical LEB128 encodings
46-
# CHECK: i16x8.any_true
47-
# CHECK-NOT: i16x8.neg
46+
# CHECK: i16x8.q15mulr_sat_s
4847
0xFD 0x82 0x81 0x80 0x80 0x80 0x80 0x00
4948

5049
# Check br_table, which has its own operand type.

‎llvm/test/MC/WebAssembly/simd-encodings.s

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -280,7 +280,8 @@ main:
280280
# CHECK: v128.bitselect # encoding: [0xfd,0x52]
281281
v128.bitselect
282282

283-
# TODO: v128.any_true # encoding: [0xfd,0x53]
283+
# CHECK: v128.any_true # encoding: [0xfd,0x53]
284+
v128.any_true
284285

285286
# CHECK: v128.load8_lane 32, 1 # encoding: [0xfd,0x54,0x00,0x20,0x01]
286287
v128.load8_lane 32, 1

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