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[RISCV] Fix isel pattern of masked vmslt[u]
This patch changes the operand order of masked vmslt[u] from (mask, rs1, scalar, maskedoff, vl) to (maskedoff, rs1, scalar, mask, vl). Reviewed By: craig.topper Differential Revision: https://reviews.llvm.org/D98839 (cherry picked from commit fca5d63)
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5 files changed

+208
-76
lines changed

5 files changed

+208
-76
lines changed

‎llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

+10-10
Original file line numberDiff line numberDiff line change
@@ -3909,10 +3909,10 @@ foreach vti = AllIntegerVectors in {
39093909
(DecImm simm5_plus1:$rs2),
39103910
GPR:$vl,
39113911
vti.SEW)>;
3912-
def : Pat<(vti.Mask (int_riscv_vmslt_mask (vti.Mask V0),
3912+
def : Pat<(vti.Mask (int_riscv_vmslt_mask (vti.Mask VR:$merge),
39133913
(vti.Vector vti.RegClass:$rs1),
39143914
(vti.Scalar simm5_plus1:$rs2),
3915-
(vti.Mask VR:$merge),
3915+
(vti.Mask V0),
39163916
(XLenVT (VLOp GPR:$vl)))),
39173917
(!cast<Instruction>("PseudoVMSLE_VI_"#vti.LMul.MX#"_MASK")
39183918
VR:$merge,
@@ -3922,17 +3922,17 @@ foreach vti = AllIntegerVectors in {
39223922
GPR:$vl,
39233923
vti.SEW)>;
39243924

3925-
def : Pat<(vti.Mask (int_riscv_vmsltu (vti.Vector vti.RegClass:$rs1),
3925+
def : Pat<(vti.Mask (int_riscv_vmsltu (vti.Vector vti.RegClass:$rs1),
39263926
(vti.Scalar simm5_plus1:$rs2),
39273927
(XLenVT (VLOp GPR:$vl)))),
39283928
(!cast<Instruction>("PseudoVMSLEU_VI_"#vti.LMul.MX) vti.RegClass:$rs1,
39293929
(DecImm simm5_plus1:$rs2),
39303930
GPR:$vl,
39313931
vti.SEW)>;
3932-
def : Pat<(vti.Mask (int_riscv_vmsltu_mask (vti.Mask V0),
3932+
def : Pat<(vti.Mask (int_riscv_vmsltu_mask (vti.Mask VR:$merge),
39333933
(vti.Vector vti.RegClass:$rs1),
39343934
(vti.Scalar simm5_plus1:$rs2),
3935-
(vti.Mask VR:$merge),
3935+
(vti.Mask V0),
39363936
(XLenVT (VLOp GPR:$vl)))),
39373937
(!cast<Instruction>("PseudoVMSLEU_VI_"#vti.LMul.MX#"_MASK")
39383938
VR:$merge,
@@ -3950,11 +3950,11 @@ foreach vti = AllIntegerVectors in {
39503950
vti.RegClass:$rs1,
39513951
GPR:$vl,
39523952
vti.SEW)>;
3953-
def : Pat<(vti.Mask (int_riscv_vmsltu_mask (vti.Mask V0),
3954-
(vti.Vector vti.RegClass:$rs1),
3955-
(vti.Scalar 0),
3956-
(vti.Mask VR:$merge),
3957-
(XLenVT (VLOp GPR:$vl)))),
3953+
def : Pat<(vti.Mask (int_riscv_vmsltu_mask (vti.Mask VR:$merge),
3954+
(vti.Vector vti.RegClass:$rs1),
3955+
(vti.Scalar 0),
3956+
(vti.Mask V0),
3957+
(XLenVT (VLOp GPR:$vl)))),
39583958
(!cast<Instruction>("PseudoVMSNE_VV_"#vti.LMul.MX#"_MASK")
39593959
VR:$merge,
39603960
vti.RegClass:$rs1,

‎llvm/test/CodeGen/RISCV/rvv/vmslt-rv32.ll

+45-15
Original file line numberDiff line numberDiff line change
@@ -1504,9 +1504,11 @@ entry:
15041504
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i8_i8(<vscale x 1 x i1> %0, <vscale x 1 x i8> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
15051505
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i8_i8:
15061506
; CHECK: # %bb.0: # %entry
1507+
; CHECK-NEXT: vmv1r.v v25, v0
15071508
; CHECK-NEXT: vsetvli a0, a0, e8,mf8,tu,mu
1508-
; CHECK-NEXT: vmsle.vi v9, v8, -15, v0.t
15091509
; CHECK-NEXT: vmv1r.v v0, v9
1510+
; CHECK-NEXT: vmsle.vi v25, v8, -15, v0.t
1511+
; CHECK-NEXT: vmv1r.v v0, v25
15101512
; CHECK-NEXT: jalr zero, 0(ra)
15111513
entry:
15121514
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i8.i8(
@@ -1537,9 +1539,11 @@ entry:
15371539
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i8_i8(<vscale x 2 x i1> %0, <vscale x 2 x i8> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
15381540
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i8_i8:
15391541
; CHECK: # %bb.0: # %entry
1542+
; CHECK-NEXT: vmv1r.v v25, v0
15401543
; CHECK-NEXT: vsetvli a0, a0, e8,mf4,tu,mu
1541-
; CHECK-NEXT: vmsle.vi v9, v8, -13, v0.t
15421544
; CHECK-NEXT: vmv1r.v v0, v9
1545+
; CHECK-NEXT: vmsle.vi v25, v8, -13, v0.t
1546+
; CHECK-NEXT: vmv1r.v v0, v25
15431547
; CHECK-NEXT: jalr zero, 0(ra)
15441548
entry:
15451549
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i8.i8(
@@ -1570,9 +1574,11 @@ entry:
15701574
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i8_i8(<vscale x 4 x i1> %0, <vscale x 4 x i8> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
15711575
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i8_i8:
15721576
; CHECK: # %bb.0: # %entry
1577+
; CHECK-NEXT: vmv1r.v v25, v0
15731578
; CHECK-NEXT: vsetvli a0, a0, e8,mf2,tu,mu
1574-
; CHECK-NEXT: vmsle.vi v9, v8, -11, v0.t
15751579
; CHECK-NEXT: vmv1r.v v0, v9
1580+
; CHECK-NEXT: vmsle.vi v25, v8, -11, v0.t
1581+
; CHECK-NEXT: vmv1r.v v0, v25
15761582
; CHECK-NEXT: jalr zero, 0(ra)
15771583
entry:
15781584
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i8.i8(
@@ -1603,9 +1609,11 @@ entry:
16031609
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i8_i8(<vscale x 8 x i1> %0, <vscale x 8 x i8> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
16041610
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i8_i8:
16051611
; CHECK: # %bb.0: # %entry
1612+
; CHECK-NEXT: vmv1r.v v25, v0
16061613
; CHECK-NEXT: vsetvli a0, a0, e8,m1,tu,mu
1607-
; CHECK-NEXT: vmsle.vi v9, v8, -9, v0.t
16081614
; CHECK-NEXT: vmv1r.v v0, v9
1615+
; CHECK-NEXT: vmsle.vi v25, v8, -9, v0.t
1616+
; CHECK-NEXT: vmv1r.v v0, v25
16091617
; CHECK-NEXT: jalr zero, 0(ra)
16101618
entry:
16111619
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i8.i8(
@@ -1636,9 +1644,11 @@ entry:
16361644
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vi_nxv16i8_i8(<vscale x 16 x i1> %0, <vscale x 16 x i8> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
16371645
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i8_i8:
16381646
; CHECK: # %bb.0: # %entry
1647+
; CHECK-NEXT: vmv1r.v v25, v0
16391648
; CHECK-NEXT: vsetvli a0, a0, e8,m2,tu,mu
1640-
; CHECK-NEXT: vmsle.vi v10, v8, -7, v0.t
16411649
; CHECK-NEXT: vmv1r.v v0, v10
1650+
; CHECK-NEXT: vmsle.vi v25, v8, -7, v0.t
1651+
; CHECK-NEXT: vmv1r.v v0, v25
16421652
; CHECK-NEXT: jalr zero, 0(ra)
16431653
entry:
16441654
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i8.i8(
@@ -1669,9 +1679,11 @@ entry:
16691679
define <vscale x 32 x i1> @intrinsic_vmslt_mask_vi_nxv32i8_i8(<vscale x 32 x i1> %0, <vscale x 32 x i8> %1, <vscale x 32 x i1> %2, i32 %3) nounwind {
16701680
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv32i8_i8:
16711681
; CHECK: # %bb.0: # %entry
1682+
; CHECK-NEXT: vmv1r.v v25, v0
16721683
; CHECK-NEXT: vsetvli a0, a0, e8,m4,tu,mu
1673-
; CHECK-NEXT: vmsle.vi v12, v8, -5, v0.t
16741684
; CHECK-NEXT: vmv1r.v v0, v12
1685+
; CHECK-NEXT: vmsle.vi v25, v8, -5, v0.t
1686+
; CHECK-NEXT: vmv1r.v v0, v25
16751687
; CHECK-NEXT: jalr zero, 0(ra)
16761688
entry:
16771689
%a = call <vscale x 32 x i1> @llvm.riscv.vmslt.mask.nxv32i8.i8(
@@ -1702,9 +1714,11 @@ entry:
17021714
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i16_i16(<vscale x 1 x i1> %0, <vscale x 1 x i16> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
17031715
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i16_i16:
17041716
; CHECK: # %bb.0: # %entry
1717+
; CHECK-NEXT: vmv1r.v v25, v0
17051718
; CHECK-NEXT: vsetvli a0, a0, e16,mf4,tu,mu
1706-
; CHECK-NEXT: vmsle.vi v9, v8, -3, v0.t
17071719
; CHECK-NEXT: vmv1r.v v0, v9
1720+
; CHECK-NEXT: vmsle.vi v25, v8, -3, v0.t
1721+
; CHECK-NEXT: vmv1r.v v0, v25
17081722
; CHECK-NEXT: jalr zero, 0(ra)
17091723
entry:
17101724
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i16.i16(
@@ -1735,9 +1749,11 @@ entry:
17351749
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i16_i16(<vscale x 2 x i1> %0, <vscale x 2 x i16> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
17361750
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i16_i16:
17371751
; CHECK: # %bb.0: # %entry
1752+
; CHECK-NEXT: vmv1r.v v25, v0
17381753
; CHECK-NEXT: vsetvli a0, a0, e16,mf2,tu,mu
1739-
; CHECK-NEXT: vmsle.vi v9, v8, -1, v0.t
17401754
; CHECK-NEXT: vmv1r.v v0, v9
1755+
; CHECK-NEXT: vmsle.vi v25, v8, -1, v0.t
1756+
; CHECK-NEXT: vmv1r.v v0, v25
17411757
; CHECK-NEXT: jalr zero, 0(ra)
17421758
entry:
17431759
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i16.i16(
@@ -1768,9 +1784,11 @@ entry:
17681784
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i16_i16(<vscale x 4 x i1> %0, <vscale x 4 x i16> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
17691785
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i16_i16:
17701786
; CHECK: # %bb.0: # %entry
1787+
; CHECK-NEXT: vmv1r.v v25, v0
17711788
; CHECK-NEXT: vsetvli a0, a0, e16,m1,tu,mu
1772-
; CHECK-NEXT: vmsle.vi v9, v8, 0, v0.t
17731789
; CHECK-NEXT: vmv1r.v v0, v9
1790+
; CHECK-NEXT: vmsle.vi v25, v8, 0, v0.t
1791+
; CHECK-NEXT: vmv1r.v v0, v25
17741792
; CHECK-NEXT: jalr zero, 0(ra)
17751793
entry:
17761794
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i16.i16(
@@ -1801,9 +1819,11 @@ entry:
18011819
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i16_i16(<vscale x 8 x i1> %0, <vscale x 8 x i16> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
18021820
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i16_i16:
18031821
; CHECK: # %bb.0: # %entry
1822+
; CHECK-NEXT: vmv1r.v v25, v0
18041823
; CHECK-NEXT: vsetvli a0, a0, e16,m2,tu,mu
1805-
; CHECK-NEXT: vmsle.vi v10, v8, 2, v0.t
18061824
; CHECK-NEXT: vmv1r.v v0, v10
1825+
; CHECK-NEXT: vmsle.vi v25, v8, 2, v0.t
1826+
; CHECK-NEXT: vmv1r.v v0, v25
18071827
; CHECK-NEXT: jalr zero, 0(ra)
18081828
entry:
18091829
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i16.i16(
@@ -1834,9 +1854,11 @@ entry:
18341854
define <vscale x 16 x i1> @intrinsic_vmslt_mask_vi_nxv16i16_i16(<vscale x 16 x i1> %0, <vscale x 16 x i16> %1, <vscale x 16 x i1> %2, i32 %3) nounwind {
18351855
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv16i16_i16:
18361856
; CHECK: # %bb.0: # %entry
1857+
; CHECK-NEXT: vmv1r.v v25, v0
18371858
; CHECK-NEXT: vsetvli a0, a0, e16,m4,tu,mu
1838-
; CHECK-NEXT: vmsle.vi v12, v8, 4, v0.t
18391859
; CHECK-NEXT: vmv1r.v v0, v12
1860+
; CHECK-NEXT: vmsle.vi v25, v8, 4, v0.t
1861+
; CHECK-NEXT: vmv1r.v v0, v25
18401862
; CHECK-NEXT: jalr zero, 0(ra)
18411863
entry:
18421864
%a = call <vscale x 16 x i1> @llvm.riscv.vmslt.mask.nxv16i16.i16(
@@ -1867,9 +1889,11 @@ entry:
18671889
define <vscale x 1 x i1> @intrinsic_vmslt_mask_vi_nxv1i32_i32(<vscale x 1 x i1> %0, <vscale x 1 x i32> %1, <vscale x 1 x i1> %2, i32 %3) nounwind {
18681890
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv1i32_i32:
18691891
; CHECK: # %bb.0: # %entry
1892+
; CHECK-NEXT: vmv1r.v v25, v0
18701893
; CHECK-NEXT: vsetvli a0, a0, e32,mf2,tu,mu
1871-
; CHECK-NEXT: vmsle.vi v9, v8, 6, v0.t
18721894
; CHECK-NEXT: vmv1r.v v0, v9
1895+
; CHECK-NEXT: vmsle.vi v25, v8, 6, v0.t
1896+
; CHECK-NEXT: vmv1r.v v0, v25
18731897
; CHECK-NEXT: jalr zero, 0(ra)
18741898
entry:
18751899
%a = call <vscale x 1 x i1> @llvm.riscv.vmslt.mask.nxv1i32.i32(
@@ -1900,9 +1924,11 @@ entry:
19001924
define <vscale x 2 x i1> @intrinsic_vmslt_mask_vi_nxv2i32_i32(<vscale x 2 x i1> %0, <vscale x 2 x i32> %1, <vscale x 2 x i1> %2, i32 %3) nounwind {
19011925
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv2i32_i32:
19021926
; CHECK: # %bb.0: # %entry
1927+
; CHECK-NEXT: vmv1r.v v25, v0
19031928
; CHECK-NEXT: vsetvli a0, a0, e32,m1,tu,mu
1904-
; CHECK-NEXT: vmsle.vi v9, v8, 8, v0.t
19051929
; CHECK-NEXT: vmv1r.v v0, v9
1930+
; CHECK-NEXT: vmsle.vi v25, v8, 8, v0.t
1931+
; CHECK-NEXT: vmv1r.v v0, v25
19061932
; CHECK-NEXT: jalr zero, 0(ra)
19071933
entry:
19081934
%a = call <vscale x 2 x i1> @llvm.riscv.vmslt.mask.nxv2i32.i32(
@@ -1933,9 +1959,11 @@ entry:
19331959
define <vscale x 4 x i1> @intrinsic_vmslt_mask_vi_nxv4i32_i32(<vscale x 4 x i1> %0, <vscale x 4 x i32> %1, <vscale x 4 x i1> %2, i32 %3) nounwind {
19341960
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv4i32_i32:
19351961
; CHECK: # %bb.0: # %entry
1962+
; CHECK-NEXT: vmv1r.v v25, v0
19361963
; CHECK-NEXT: vsetvli a0, a0, e32,m2,tu,mu
1937-
; CHECK-NEXT: vmsle.vi v10, v8, 10, v0.t
19381964
; CHECK-NEXT: vmv1r.v v0, v10
1965+
; CHECK-NEXT: vmsle.vi v25, v8, 10, v0.t
1966+
; CHECK-NEXT: vmv1r.v v0, v25
19391967
; CHECK-NEXT: jalr zero, 0(ra)
19401968
entry:
19411969
%a = call <vscale x 4 x i1> @llvm.riscv.vmslt.mask.nxv4i32.i32(
@@ -1966,9 +1994,11 @@ entry:
19661994
define <vscale x 8 x i1> @intrinsic_vmslt_mask_vi_nxv8i32_i32(<vscale x 8 x i1> %0, <vscale x 8 x i32> %1, <vscale x 8 x i1> %2, i32 %3) nounwind {
19671995
; CHECK-LABEL: intrinsic_vmslt_mask_vi_nxv8i32_i32:
19681996
; CHECK: # %bb.0: # %entry
1997+
; CHECK-NEXT: vmv1r.v v25, v0
19691998
; CHECK-NEXT: vsetvli a0, a0, e32,m4,tu,mu
1970-
; CHECK-NEXT: vmsle.vi v12, v8, 12, v0.t
19711999
; CHECK-NEXT: vmv1r.v v0, v12
2000+
; CHECK-NEXT: vmsle.vi v25, v8, 12, v0.t
2001+
; CHECK-NEXT: vmv1r.v v0, v25
19722002
; CHECK-NEXT: jalr zero, 0(ra)
19732003
entry:
19742004
%a = call <vscale x 8 x i1> @llvm.riscv.vmslt.mask.nxv8i32.i32(

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