[CodeGen] Rename RegisterMaskPair to VRegMaskOrUnit. NFC (llvm#123799)

This holds a physical register unit or virtual register and mask.

While I was here I've used emplace_back and removed an unneeded use of a
template.

Author: topperc

llvm/include/llvm/CodeGen/MachineScheduler.h

@@ -525,7 +525,7 @@ class ScheduleDAGMILive : public ScheduleDAGMI {
 
   void initRegPressure();
 
-  void updatePressureDiffs(ArrayRef<RegisterMaskPair> LiveUses);
+  void updatePressureDiffs(ArrayRef<VRegMaskOrUnit> LiveUses);
 
   void updateScheduledPressure(const SUnit *SU,
                                const std::vector<unsigned> &NewMaxPressure);

llvm/include/llvm/CodeGen/RegisterPressure.h

@@ -35,11 +35,11 @@ class MachineInstr;
 class MachineRegisterInfo;
 class RegisterClassInfo;
 
-struct RegisterMaskPair {
+struct VRegMaskOrUnit {
   Register RegUnit; ///< Virtual register or register unit.
   LaneBitmask LaneMask;
 
-  RegisterMaskPair(Register RegUnit, LaneBitmask LaneMask)
+  VRegMaskOrUnit(Register RegUnit, LaneBitmask LaneMask)
       : RegUnit(RegUnit), LaneMask(LaneMask) {}
 };
 
@@ -49,8 +49,8 @@ struct RegisterPressure {
   std::vector<unsigned> MaxSetPressure;
 
   /// List of live in virtual registers or physical register units.
-  SmallVector<RegisterMaskPair,8> LiveInRegs;
-  SmallVector<RegisterMaskPair,8> LiveOutRegs;
+  SmallVector<VRegMaskOrUnit, 8> LiveInRegs;
+  SmallVector<VRegMaskOrUnit, 8> LiveOutRegs;
 
   void dump(const TargetRegisterInfo *TRI) const;
 };
@@ -166,13 +166,13 @@ class PressureDiff {
 class RegisterOperands {
 public:
   /// List of virtual registers and register units read by the instruction.
-  SmallVector<RegisterMaskPair, 8> Uses;
+  SmallVector<VRegMaskOrUnit, 8> Uses;
   /// List of virtual registers and register units defined by the
   /// instruction which are not dead.
-  SmallVector<RegisterMaskPair, 8> Defs;
+  SmallVector<VRegMaskOrUnit, 8> Defs;
   /// List of virtual registers and register units defined by the
   /// instruction but dead.
-  SmallVector<RegisterMaskPair, 8> DeadDefs;
+  SmallVector<VRegMaskOrUnit, 8> DeadDefs;
 
   /// Analyze the given instruction \p MI and fill in the Uses, Defs and
   /// DeadDefs list based on the MachineOperand flags.
@@ -185,7 +185,7 @@ class RegisterOperands {
   void detectDeadDefs(const MachineInstr &MI, const LiveIntervals &LIS);
 
   /// Use liveness information to find out which uses/defs are partially
-  /// undefined/dead and adjust the RegisterMaskPairs accordingly.
+  /// undefined/dead and adjust the VRegMaskOrUnits accordingly.
   /// If \p AddFlagsMI is given then missing read-undef and dead flags will be
   /// added to the instruction.
   void adjustLaneLiveness(const LiveIntervals &LIS,
@@ -303,7 +303,7 @@ class LiveRegSet {
 
   /// Mark the \p Pair.LaneMask lanes of \p Pair.Reg as live.
   /// Returns the previously live lanes of \p Pair.Reg.
-  LaneBitmask insert(RegisterMaskPair Pair) {
+  LaneBitmask insert(VRegMaskOrUnit Pair) {
     unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
     auto InsertRes = Regs.insert(IndexMaskPair(SparseIndex, Pair.LaneMask));
     if (!InsertRes.second) {
@@ -316,7 +316,7 @@ class LiveRegSet {
 
   /// Clears the \p Pair.LaneMask lanes of \p Pair.Reg (mark them as dead).
   /// Returns the previously live lanes of \p Pair.Reg.
-  LaneBitmask erase(RegisterMaskPair Pair) {
+  LaneBitmask erase(VRegMaskOrUnit Pair) {
     unsigned SparseIndex = getSparseIndexFromReg(Pair.RegUnit);
     RegSet::iterator I = Regs.find(SparseIndex);
     if (I == Regs.end())
@@ -330,12 +330,11 @@ class LiveRegSet {
     return Regs.size();
   }
 
-  template<typename ContainerT>
-  void appendTo(ContainerT &To) const {
+  void appendTo(SmallVectorImpl<VRegMaskOrUnit> &To) const {
     for (const IndexMaskPair &P : Regs) {
       Register Reg = getRegFromSparseIndex(P.Index);
       if (P.LaneMask.any())
-        To.push_back(RegisterMaskPair(Reg, P.LaneMask));
+        To.emplace_back(Reg, P.LaneMask);
     }
   }
 };
@@ -409,7 +408,7 @@ class RegPressureTracker {
   /// Force liveness of virtual registers or physical register
   /// units. Particularly useful to initialize the livein/out state of the
   /// tracker before the first call to advance/recede.
-  void addLiveRegs(ArrayRef<RegisterMaskPair> Regs);
+  void addLiveRegs(ArrayRef<VRegMaskOrUnit> Regs);
 
   /// Get the MI position corresponding to this register pressure.
   MachineBasicBlock::const_iterator getPos() const { return CurrPos; }
@@ -421,14 +420,14 @@ class RegPressureTracker {
   void setPos(MachineBasicBlock::const_iterator Pos) { CurrPos = Pos; }
 
   /// Recede across the previous instruction.
-  void recede(SmallVectorImpl<RegisterMaskPair> *LiveUses = nullptr);
+  void recede(SmallVectorImpl<VRegMaskOrUnit> *LiveUses = nullptr);
 
   /// Recede across the previous instruction.
   /// This "low-level" variant assumes that recedeSkipDebugValues() was
   /// called previously and takes precomputed RegisterOperands for the
   /// instruction.
   void recede(const RegisterOperands &RegOpers,
-              SmallVectorImpl<RegisterMaskPair> *LiveUses = nullptr);
+              SmallVectorImpl<VRegMaskOrUnit> *LiveUses = nullptr);
 
   /// Recede until we find an instruction which is not a DebugValue.
   void recedeSkipDebugValues();
@@ -546,21 +545,21 @@ class RegPressureTracker {
 
 protected:
   /// Add Reg to the live out set and increase max pressure.
-  void discoverLiveOut(RegisterMaskPair Pair);
+  void discoverLiveOut(VRegMaskOrUnit Pair);
   /// Add Reg to the live in set and increase max pressure.
-  void discoverLiveIn(RegisterMaskPair Pair);
+  void discoverLiveIn(VRegMaskOrUnit Pair);
 
   /// Get the SlotIndex for the first nondebug instruction including or
   /// after the current position.
   SlotIndex getCurrSlot() const;
 
-  void bumpDeadDefs(ArrayRef<RegisterMaskPair> DeadDefs);
+  void bumpDeadDefs(ArrayRef<VRegMaskOrUnit> DeadDefs);
 
   void bumpUpwardPressure(const MachineInstr *MI);
   void bumpDownwardPressure(const MachineInstr *MI);
 
-  void discoverLiveInOrOut(RegisterMaskPair Pair,
-                           SmallVectorImpl<RegisterMaskPair> &LiveInOrOut);
+  void discoverLiveInOrOut(VRegMaskOrUnit Pair,
+                           SmallVectorImpl<VRegMaskOrUnit> &LiveInOrOut);
 
   LaneBitmask getLastUsedLanes(Register RegUnit, SlotIndex Pos) const;
   LaneBitmask getLiveLanesAt(Register RegUnit, SlotIndex Pos) const;

llvm/lib/CodeGen/MachinePipeliner.cpp

@@ -1981,7 +1981,7 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
                             NodeSet &NS) {
   const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
   MachineRegisterInfo &MRI = MF.getRegInfo();
-  SmallVector<RegisterMaskPair, 8> LiveOutRegs;
+  SmallVector<VRegMaskOrUnit, 8> LiveOutRegs;
   SmallSet<unsigned, 4> Uses;
   for (SUnit *SU : NS) {
     const MachineInstr *MI = SU->getInstr();
@@ -2002,13 +2002,11 @@ static void computeLiveOuts(MachineFunction &MF, RegPressureTracker &RPTracker,
         Register Reg = MO.getReg();
         if (Reg.isVirtual()) {
           if (!Uses.count(Reg))
-            LiveOutRegs.push_back(RegisterMaskPair(Reg,
-                                                   LaneBitmask::getNone()));
+            LiveOutRegs.emplace_back(Reg, LaneBitmask::getNone());
         } else if (MRI.isAllocatable(Reg)) {
           for (MCRegUnit Unit : TRI->regunits(Reg.asMCReg()))
             if (!Uses.count(Unit))
-              LiveOutRegs.push_back(
-                  RegisterMaskPair(Unit, LaneBitmask::getNone()));
+              LiveOutRegs.emplace_back(Unit, LaneBitmask::getNone());
         }
       }
   RPTracker.addLiveRegs(LiveOutRegs);

llvm/lib/CodeGen/MachineScheduler.cpp

@@ -1288,7 +1288,7 @@ void ScheduleDAGMILive::initRegPressure() {
 
   // Account for liveness generated by the region boundary.
   if (LiveRegionEnd != RegionEnd) {
-    SmallVector<RegisterMaskPair, 8> LiveUses;
+    SmallVector<VRegMaskOrUnit, 8> LiveUses;
     BotRPTracker.recede(&LiveUses);
     updatePressureDiffs(LiveUses);
   }
@@ -1352,9 +1352,8 @@ updateScheduledPressure(const SUnit *SU,
 
 /// Update the PressureDiff array for liveness after scheduling this
 /// instruction.
-void ScheduleDAGMILive::updatePressureDiffs(
-    ArrayRef<RegisterMaskPair> LiveUses) {
-  for (const RegisterMaskPair &P : LiveUses) {
+void ScheduleDAGMILive::updatePressureDiffs(ArrayRef<VRegMaskOrUnit> LiveUses) {
+  for (const VRegMaskOrUnit &P : LiveUses) {
     Register Reg = P.RegUnit;
     /// FIXME: Currently assuming single-use physregs.
     if (!Reg.isVirtual())
@@ -1579,7 +1578,7 @@ unsigned ScheduleDAGMILive::computeCyclicCriticalPath() {
 
   unsigned MaxCyclicLatency = 0;
   // Visit each live out vreg def to find def/use pairs that cross iterations.
-  for (const RegisterMaskPair &P : RPTracker.getPressure().LiveOutRegs) {
+  for (const VRegMaskOrUnit &P : RPTracker.getPressure().LiveOutRegs) {
     Register Reg = P.RegUnit;
     if (!Reg.isVirtual())
       continue;
@@ -1707,7 +1706,7 @@ void ScheduleDAGMILive::scheduleMI(SUnit *SU, bool IsTopNode) {
 
       if (BotRPTracker.getPos() != CurrentBottom)
         BotRPTracker.recedeSkipDebugValues();
-      SmallVector<RegisterMaskPair, 8> LiveUses;
+      SmallVector<VRegMaskOrUnit, 8> LiveUses;
       BotRPTracker.recede(RegOpers, &LiveUses);
       assert(BotRPTracker.getPos() == CurrentBottom && "out of sync");
       LLVM_DEBUG(dbgs() << "Bottom Pressure:\n"; dumpRegSetPressure(