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vitalybuka
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tru
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Revert "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting"
And dependent commits. Details in D150388. This reverts commit 825b7f0. This reverts commit 7a98f08. This reverts commit b4a62b1. This reverts commit b7836d8. No conflicts in the code, few tests had conflicts in autogenerated CHECKs: llvm/test/CodeGen/Thumb2/mve-float32regloops.ll llvm/test/CodeGen/AMDGPU/fix-frame-reg-in-custom-csr-spills.ll Reviewed By: alexfh Differential Revision: https://reviews.llvm.org/D156381 (cherry picked from commit a496c8b)
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‎llvm/include/llvm/CodeGen/TargetInstrInfo.h

Lines changed: 0 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -1044,16 +1044,6 @@ class TargetInstrInfo : public MCInstrInfo {
10441044
return isCopyInstrImpl(MI);
10451045
}
10461046

1047-
bool isFullCopyInstr(const MachineInstr &MI) const {
1048-
auto DestSrc = isCopyInstr(MI);
1049-
if (!DestSrc)
1050-
return false;
1051-
1052-
const MachineOperand *DestRegOp = DestSrc->Destination;
1053-
const MachineOperand *SrcRegOp = DestSrc->Source;
1054-
return !DestRegOp->getSubReg() && !SrcRegOp->getSubReg();
1055-
}
1056-
10571047
/// If the specific machine instruction is an instruction that adds an
10581048
/// immediate value and a physical register, and stores the result in
10591049
/// the given physical register \c Reg, return a pair of the source
@@ -1968,13 +1958,6 @@ class TargetInstrInfo : public MCInstrInfo {
19681958
return false;
19691959
}
19701960

1971-
/// Allows targets to use appropriate copy instruction while spilitting live
1972-
/// range of a register in register allocation.
1973-
virtual unsigned getLiveRangeSplitOpcode(Register Reg,
1974-
const MachineFunction &MF) const {
1975-
return TargetOpcode::COPY;
1976-
}
1977-
19781961
/// During PHI eleimination lets target to make necessary checks and
19791962
/// insert the copy to the PHI destination register in a target specific
19801963
/// manner.

‎llvm/lib/CodeGen/CalcSpillWeights.cpp

Lines changed: 3 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -97,7 +97,7 @@ bool VirtRegAuxInfo::isRematerializable(const LiveInterval &LI,
9797
// Trace copies introduced by live range splitting. The inline
9898
// spiller can rematerialize through these copies, so the spill
9999
// weight must reflect this.
100-
while (TII.isFullCopyInstr(*MI)) {
100+
while (MI->isFullCopy()) {
101101
// The copy destination must match the interval register.
102102
if (MI->getOperand(0).getReg() != Reg)
103103
return false;
@@ -224,16 +224,7 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &LI, SlotIndex *Start,
224224
continue;
225225

226226
NumInstr++;
227-
bool identityCopy = false;
228-
auto DestSrc = TII.isCopyInstr(*MI);
229-
if (DestSrc) {
230-
const MachineOperand *DestRegOp = DestSrc->Destination;
231-
const MachineOperand *SrcRegOp = DestSrc->Source;
232-
identityCopy = DestRegOp->getReg() == SrcRegOp->getReg() &&
233-
DestRegOp->getSubReg() == SrcRegOp->getSubReg();
234-
}
235-
236-
if (identityCopy || MI->isImplicitDef())
227+
if (MI->isIdentityCopy() || MI->isImplicitDef())
237228
continue;
238229
if (!Visited.insert(MI).second)
239230
continue;
@@ -267,7 +258,7 @@ float VirtRegAuxInfo::weightCalcHelper(LiveInterval &LI, SlotIndex *Start,
267258
}
268259

269260
// Get allocation hints from copies.
270-
if (!TII.isCopyInstr(*MI))
261+
if (!MI->isCopy())
271262
continue;
272263
Register HintReg = copyHint(MI, LI.reg(), TRI, MRI);
273264
if (!HintReg)

‎llvm/lib/CodeGen/InlineSpiller.cpp

Lines changed: 16 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -256,11 +256,11 @@ Spiller *llvm::createInlineSpiller(MachineFunctionPass &Pass,
256256
// This minimizes register pressure and maximizes the store-to-load distance for
257257
// spill slots which can be important in tight loops.
258258

259-
/// isFullCopyOf - If MI is a COPY to or from Reg, return the other register,
260-
/// otherwise return 0.
261-
static Register isCopyOf(const MachineInstr &MI, Register Reg,
262-
const TargetInstrInfo &TII) {
263-
if (!TII.isCopyInstr(MI))
259+
/// If MI is a COPY to or from Reg, return the other register, otherwise return
260+
/// 0.
261+
static Register isCopyOf(const MachineInstr &MI, Register Reg) {
262+
assert(!MI.isBundled());
263+
if (!MI.isCopy())
264264
return Register();
265265

266266
const MachineOperand &DstOp = MI.getOperand(0);
@@ -277,10 +277,9 @@ static Register isCopyOf(const MachineInstr &MI, Register Reg,
277277
}
278278

279279
/// Check for a copy bundle as formed by SplitKit.
280-
static Register isCopyOfBundle(const MachineInstr &FirstMI, Register Reg,
281-
const TargetInstrInfo &TII) {
280+
static Register isCopyOfBundle(const MachineInstr &FirstMI, Register Reg) {
282281
if (!FirstMI.isBundled())
283-
return isCopyOf(FirstMI, Reg, TII);
282+
return isCopyOf(FirstMI, Reg);
284283

285284
assert(!FirstMI.isBundledWithPred() && FirstMI.isBundledWithSucc() &&
286285
"expected to see first instruction in bundle");
@@ -289,12 +288,11 @@ static Register isCopyOfBundle(const MachineInstr &FirstMI, Register Reg,
289288
MachineBasicBlock::const_instr_iterator I = FirstMI.getIterator();
290289
while (I->isBundledWithSucc()) {
291290
const MachineInstr &MI = *I;
292-
auto CopyInst = TII.isCopyInstr(MI);
293-
if (!CopyInst)
291+
if (!MI.isCopy())
294292
return Register();
295293

296-
const MachineOperand &DstOp = *CopyInst->Destination;
297-
const MachineOperand &SrcOp = *CopyInst->Source;
294+
const MachineOperand &DstOp = MI.getOperand(0);
295+
const MachineOperand &SrcOp = MI.getOperand(1);
298296
if (DstOp.getReg() == Reg) {
299297
if (!SnipReg)
300298
SnipReg = SrcOp.getReg();
@@ -360,7 +358,7 @@ bool InlineSpiller::isSnippet(const LiveInterval &SnipLI) {
360358
MachineInstr &MI = *RI++;
361359

362360
// Allow copies to/from Reg.
363-
if (isCopyOfBundle(MI, Reg, TII))
361+
if (isCopyOfBundle(MI, Reg))
364362
continue;
365363

366364
// Allow stack slot loads.
@@ -398,7 +396,7 @@ void InlineSpiller::collectRegsToSpill() {
398396
return;
399397

400398
for (MachineInstr &MI : llvm::make_early_inc_range(MRI.reg_bundles(Reg))) {
401-
Register SnipReg = isCopyOfBundle(MI, Reg, TII);
399+
Register SnipReg = isCopyOfBundle(MI, Reg);
402400
if (!isSibling(SnipReg))
403401
continue;
404402
LiveInterval &SnipLI = LIS.getInterval(SnipReg);
@@ -521,14 +519,14 @@ void InlineSpiller::eliminateRedundantSpills(LiveInterval &SLI, VNInfo *VNI) {
521519
// Find all spills and copies of VNI.
522520
for (MachineInstr &MI :
523521
llvm::make_early_inc_range(MRI.use_nodbg_bundles(Reg))) {
524-
if (!MI.mayStore() && !TII.isCopyInstr(MI))
522+
if (!MI.isCopy() && !MI.mayStore())
525523
continue;
526524
SlotIndex Idx = LIS.getInstructionIndex(MI);
527525
if (LI->getVNInfoAt(Idx) != VNI)
528526
continue;
529527

530528
// Follow sibling copies down the dominator tree.
531-
if (Register DstReg = isCopyOfBundle(MI, Reg, TII)) {
529+
if (Register DstReg = isCopyOfBundle(MI, Reg)) {
532530
if (isSibling(DstReg)) {
533531
LiveInterval &DstLI = LIS.getInterval(DstReg);
534532
VNInfo *DstVNI = DstLI.getVNInfoAt(Idx.getRegSlot());
@@ -872,7 +870,7 @@ foldMemoryOperand(ArrayRef<std::pair<MachineInstr *, unsigned>> Ops,
872870
if (Ops.back().first != MI || MI->isBundled())
873871
return false;
874872

875-
bool WasCopy = TII.isCopyInstr(*MI).has_value();
873+
bool WasCopy = MI->isCopy();
876874
Register ImpReg;
877875

878876
// TII::foldMemoryOperand will do what we need here for statepoint
@@ -1157,7 +1155,7 @@ void InlineSpiller::spillAroundUses(Register Reg) {
11571155
Idx = VNI->def;
11581156

11591157
// Check for a sibling copy.
1160-
Register SibReg = isCopyOfBundle(MI, Reg, TII);
1158+
Register SibReg = isCopyOfBundle(MI, Reg);
11611159
if (SibReg && isSibling(SibReg)) {
11621160
// This may actually be a copy between snippets.
11631161
if (isRegToSpill(SibReg)) {

‎llvm/lib/CodeGen/LiveRangeEdit.cpp

Lines changed: 1 addition & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -352,8 +352,7 @@ void LiveRangeEdit::eliminateDeadDef(MachineInstr *MI, ToShrinkSet &ToShrink) {
352352
// unlikely to change anything. We typically don't want to shrink the
353353
// PIC base register that has lots of uses everywhere.
354354
// Always shrink COPY uses that probably come from live range splitting.
355-
if ((MI->readsVirtualRegister(Reg) &&
356-
(MO.isDef() || TII.isCopyInstr(*MI))) ||
355+
if ((MI->readsVirtualRegister(Reg) && (MI->isCopy() || MO.isDef())) ||
357356
(MO.readsReg() && (MRI.hasOneNonDBGUse(Reg) || useIsKill(LI, MO))))
358357
ToShrink.insert(&LI);
359358
else if (MO.readsReg())

‎llvm/lib/CodeGen/LiveRangeShrink.cpp

Lines changed: 1 addition & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,6 @@
2323
#include "llvm/CodeGen/MachineInstr.h"
2424
#include "llvm/CodeGen/MachineOperand.h"
2525
#include "llvm/CodeGen/MachineRegisterInfo.h"
26-
#include "llvm/CodeGen/TargetInstrInfo.h"
2726
#include "llvm/InitializePasses.h"
2827
#include "llvm/Pass.h"
2928
#include "llvm/Support/Debug.h"
@@ -110,7 +109,6 @@ bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) {
110109
return false;
111110

112111
MachineRegisterInfo &MRI = MF.getRegInfo();
113-
const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
114112

115113
LLVM_DEBUG(dbgs() << "**** Analysing " << MF.getName() << '\n');
116114

@@ -199,7 +197,7 @@ bool LiveRangeShrink::runOnMachineFunction(MachineFunction &MF) {
199197
// is because it needs more accurate model to handle register
200198
// pressure correctly.
201199
MachineInstr &DefInstr = *MRI.def_instr_begin(Reg);
202-
if (!TII.isCopyInstr(DefInstr))
200+
if (!DefInstr.isCopy())
203201
NumEligibleUse++;
204202
Insert = FindDominatedInstruction(DefInstr, Insert, IOM);
205203
} else {

‎llvm/lib/CodeGen/RegAllocGreedy.cpp

Lines changed: 9 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -1282,12 +1282,10 @@ static LaneBitmask getInstReadLaneMask(const MachineRegisterInfo &MRI,
12821282
/// VirtReg.
12831283
static bool readsLaneSubset(const MachineRegisterInfo &MRI,
12841284
const MachineInstr *MI, const LiveInterval &VirtReg,
1285-
const TargetRegisterInfo *TRI, SlotIndex Use,
1286-
const TargetInstrInfo *TII) {
1285+
const TargetRegisterInfo *TRI, SlotIndex Use) {
12871286
// Early check the common case.
1288-
auto DestSrc = TII->isCopyInstr(*MI);
1289-
if (DestSrc &&
1290-
DestSrc->Destination->getSubReg() == DestSrc->Source->getSubReg())
1287+
if (MI->isCopy() &&
1288+
MI->getOperand(0).getSubReg() == MI->getOperand(1).getSubReg())
12911289
return false;
12921290

12931291
// FIXME: We're only considering uses, but should be consider defs too?
@@ -1346,14 +1344,14 @@ unsigned RAGreedy::tryInstructionSplit(const LiveInterval &VirtReg,
13461344
// the allocation.
13471345
for (const SlotIndex Use : Uses) {
13481346
if (const MachineInstr *MI = Indexes->getInstructionFromIndex(Use)) {
1349-
if (TII->isFullCopyInstr(*MI) ||
1347+
if (MI->isFullCopy() ||
13501348
(SplitSubClass &&
13511349
SuperRCNumAllocatableRegs ==
13521350
getNumAllocatableRegsForConstraints(MI, VirtReg.reg(), SuperRC,
13531351
TII, TRI, RegClassInfo)) ||
13541352
// TODO: Handle split for subranges with subclass constraints?
13551353
(!SplitSubClass && VirtReg.hasSubRanges() &&
1356-
!readsLaneSubset(*MRI, MI, VirtReg, TRI, Use, TII))) {
1354+
!readsLaneSubset(*MRI, MI, VirtReg, TRI, Use))) {
13571355
LLVM_DEBUG(dbgs() << " skip:\t" << Use << '\t' << *MI);
13581356
continue;
13591357
}
@@ -2140,7 +2138,7 @@ void RAGreedy::initializeCSRCost() {
21402138
/// \p Out is not cleared before being populated.
21412139
void RAGreedy::collectHintInfo(Register Reg, HintsInfo &Out) {
21422140
for (const MachineInstr &Instr : MRI->reg_nodbg_instructions(Reg)) {
2143-
if (!TII->isFullCopyInstr(Instr))
2141+
if (!Instr.isFullCopy())
21442142
continue;
21452143
// Look for the other end of the copy.
21462144
Register OtherReg = Instr.getOperand(0).getReg();
@@ -2455,10 +2453,9 @@ RAGreedy::RAGreedyStats RAGreedy::computeStats(MachineBasicBlock &MBB) {
24552453
MI.getOpcode() == TargetOpcode::STATEPOINT;
24562454
};
24572455
for (MachineInstr &MI : MBB) {
2458-
auto DestSrc = TII->isCopyInstr(MI);
2459-
if (DestSrc) {
2460-
const MachineOperand &Dest = *DestSrc->Destination;
2461-
const MachineOperand &Src = *DestSrc->Source;
2456+
if (MI.isCopy()) {
2457+
const MachineOperand &Dest = MI.getOperand(0);
2458+
const MachineOperand &Src = MI.getOperand(1);
24622459
Register SrcReg = Src.getReg();
24632460
Register DestReg = Dest.getReg();
24642461
// Only count `COPY`s with a virtual register as source or destination.

‎llvm/lib/CodeGen/SplitKit.cpp

Lines changed: 7 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -514,10 +514,10 @@ void SplitEditor::forceRecompute(unsigned RegIdx, const VNInfo &ParentVNI) {
514514
VFP = ValueForcePair(nullptr, true);
515515
}
516516

517-
SlotIndex SplitEditor::buildSingleSubRegCopy(
518-
Register FromReg, Register ToReg, MachineBasicBlock &MBB,
519-
MachineBasicBlock::iterator InsertBefore, unsigned SubIdx,
520-
LiveInterval &DestLI, bool Late, SlotIndex Def, const MCInstrDesc &Desc) {
517+
SlotIndex SplitEditor::buildSingleSubRegCopy(Register FromReg, Register ToReg,
518+
MachineBasicBlock &MBB, MachineBasicBlock::iterator InsertBefore,
519+
unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def) {
520+
const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
521521
bool FirstCopy = !Def.isValid();
522522
MachineInstr *CopyMI = BuildMI(MBB, InsertBefore, DebugLoc(), Desc)
523523
.addReg(ToReg, RegState::Define | getUndefRegState(FirstCopy)
@@ -536,8 +536,7 @@ SlotIndex SplitEditor::buildSingleSubRegCopy(
536536
SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg,
537537
LaneBitmask LaneMask, MachineBasicBlock &MBB,
538538
MachineBasicBlock::iterator InsertBefore, bool Late, unsigned RegIdx) {
539-
const MCInstrDesc &Desc =
540-
TII.get(TII.getLiveRangeSplitOpcode(FromReg, *MBB.getParent()));
539+
const MCInstrDesc &Desc = TII.get(TargetOpcode::COPY);
541540
SlotIndexes &Indexes = *LIS.getSlotIndexes();
542541
if (LaneMask.all() || LaneMask == MRI.getMaxLaneMaskForVReg(FromReg)) {
543542
// The full vreg is copied.
@@ -565,7 +564,7 @@ SlotIndex SplitEditor::buildCopy(Register FromReg, Register ToReg,
565564
SlotIndex Def;
566565
for (unsigned BestIdx : SubIndexes) {
567566
Def = buildSingleSubRegCopy(FromReg, ToReg, MBB, InsertBefore, BestIdx,
568-
DestLI, Late, Def, Desc);
567+
DestLI, Late, Def);
569568
}
570569

571570
BumpPtrAllocator &Allocator = LIS.getVNInfoAllocator();
@@ -1585,9 +1584,7 @@ bool SplitAnalysis::shouldSplitSingleBlock(const BlockInfo &BI,
15851584
if (BI.LiveIn && BI.LiveOut)
15861585
return true;
15871586
// No point in isolating a copy. It has no register class constraints.
1588-
MachineInstr *MI = LIS.getInstructionFromIndex(BI.FirstInstr);
1589-
bool copyLike = TII.isCopyInstr(*MI) || MI->isSubregToReg();
1590-
if (copyLike)
1587+
if (LIS.getInstructionFromIndex(BI.FirstInstr)->isCopyLike())
15911588
return false;
15921589
// Finally, don't isolate an end point that was created by earlier splits.
15931590
return isOriginalEndpoint(BI.FirstInstr);

‎llvm/lib/CodeGen/SplitKit.h

Lines changed: 2 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -428,11 +428,8 @@ class LLVM_LIBRARY_VISIBILITY SplitEditor {
428428
bool Late, unsigned RegIdx);
429429

430430
SlotIndex buildSingleSubRegCopy(Register FromReg, Register ToReg,
431-
MachineBasicBlock &MB,
432-
MachineBasicBlock::iterator InsertBefore,
433-
unsigned SubIdx, LiveInterval &DestLI,
434-
bool Late, SlotIndex Def,
435-
const MCInstrDesc &Desc);
431+
MachineBasicBlock &MB, MachineBasicBlock::iterator InsertBefore,
432+
unsigned SubIdx, LiveInterval &DestLI, bool Late, SlotIndex Def);
436433

437434
public:
438435
/// Create a new SplitEditor for editing the LiveInterval analyzed by SA.

‎llvm/lib/CodeGen/TargetInstrInfo.cpp

Lines changed: 3 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -440,9 +440,8 @@ MachineInstr &TargetInstrInfo::duplicate(MachineBasicBlock &MBB,
440440
// If the COPY instruction in MI can be folded to a stack operation, return
441441
// the register class to use.
442442
static const TargetRegisterClass *canFoldCopy(const MachineInstr &MI,
443-
const TargetInstrInfo &TII,
444443
unsigned FoldIdx) {
445-
assert(TII.isCopyInstr(MI) && "MI must be a COPY instruction");
444+
assert(MI.isCopy() && "MI must be a COPY instruction");
446445
if (MI.getNumOperands() != 2)
447446
return nullptr;
448447
assert(FoldIdx<2 && "FoldIdx refers no nonexistent operand");
@@ -631,10 +630,10 @@ MachineInstr *TargetInstrInfo::foldMemoryOperand(MachineInstr &MI,
631630
}
632631

633632
// Straight COPY may fold as load/store.
634-
if (!isCopyInstr(MI) || Ops.size() != 1)
633+
if (!MI.isCopy() || Ops.size() != 1)
635634
return nullptr;
636635

637-
const TargetRegisterClass *RC = canFoldCopy(MI, *this, Ops[0]);
636+
const TargetRegisterClass *RC = canFoldCopy(MI, Ops[0]);
638637
if (!RC)
639638
return nullptr;
640639

‎llvm/lib/Target/AMDGPU/AMDGPU.h

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -41,7 +41,6 @@ FunctionPass *createSIFixControlFlowLiveIntervalsPass();
4141
FunctionPass *createSIOptimizeExecMaskingPreRAPass();
4242
FunctionPass *createSIOptimizeVGPRLiveRangePass();
4343
FunctionPass *createSIFixSGPRCopiesPass();
44-
FunctionPass *createLowerWWMCopiesPass();
4544
FunctionPass *createSIMemoryLegalizerPass();
4645
FunctionPass *createSIInsertWaitcntsPass();
4746
FunctionPass *createSIPreAllocateWWMRegsPass();
@@ -145,9 +144,6 @@ extern char &SIFixSGPRCopiesID;
145144
void initializeSIFixVGPRCopiesPass(PassRegistry &);
146145
extern char &SIFixVGPRCopiesID;
147146

148-
void initializeSILowerWWMCopiesPass(PassRegistry &);
149-
extern char &SILowerWWMCopiesID;
150-
151147
void initializeSILowerI1CopiesPass(PassRegistry &);
152148
extern char &SILowerI1CopiesID;
153149

‎llvm/lib/Target/AMDGPU/AMDGPUTargetMachine.cpp

Lines changed: 0 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -364,7 +364,6 @@ extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeAMDGPUTarget() {
364364
initializeAMDGPUDAGToDAGISelPass(*PR);
365365
initializeGCNDPPCombinePass(*PR);
366366
initializeSILowerI1CopiesPass(*PR);
367-
initializeSILowerWWMCopiesPass(*PR);
368367
initializeSILowerSGPRSpillsPass(*PR);
369368
initializeSIFixSGPRCopiesPass(*PR);
370369
initializeSIFixVGPRCopiesPass(*PR);
@@ -1297,7 +1296,6 @@ void GCNPassConfig::addOptimizedRegAlloc() {
12971296
}
12981297

12991298
bool GCNPassConfig::addPreRewrite() {
1300-
addPass(&SILowerWWMCopiesID);
13011299
if (EnableRegReassign)
13021300
addPass(&GCNNSAReassignID);
13031301
return true;
@@ -1352,8 +1350,6 @@ bool GCNPassConfig::addRegAssignAndRewriteFast() {
13521350
addPass(&SILowerSGPRSpillsID);
13531351

13541352
addPass(createVGPRAllocPass(false));
1355-
1356-
addPass(&SILowerWWMCopiesID);
13571353
return true;
13581354
}
13591355

‎llvm/lib/Target/AMDGPU/CMakeLists.txt

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -145,7 +145,6 @@ add_llvm_target(AMDGPUCodeGen
145145
SILoadStoreOptimizer.cpp
146146
SILowerControlFlow.cpp
147147
SILowerI1Copies.cpp
148-
SILowerWWMCopies.cpp
149148
SILowerSGPRSpills.cpp
150149
SIMachineFunctionInfo.cpp
151150
SIMachineScheduler.cpp

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