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Commit 71947ed

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Jessica Paquette
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[AArch64][GlobalISel] Constrain reg operands in selectBrJT
This was causing a machine verifier failure on the test suite. Make sure that we don't end up with a weird register class here. Failure for reference: *** Bad machine code: Illegal virtual register for instruction *** - function: check_constrain - basic block: %bb.1 (0x7f8b70839f80) - instruction: early-clobber %6:gpr64, early-clobber %7:gpr64sp = JumpTableDest32 %5:gpr64, %1:gpr64sp, %jump-table.0 - operand 3: %1:gpr64sp Expected a GPR64 register, but got a GPR64sp register Differential Revision: https://reviews.llvm.org/D77349
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llvm/lib/Target/AArch64/AArch64InstructionSelector.cpp

Lines changed: 4 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -2766,14 +2766,13 @@ bool AArch64InstructionSelector::selectBrJT(MachineInstr &I,
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Register TargetReg = MRI.createVirtualRegister(&AArch64::GPR64RegClass);
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Register ScratchReg = MRI.createVirtualRegister(&AArch64::GPR64spRegClass);
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MIB.buildInstr(AArch64::JumpTableDest32, {TargetReg, ScratchReg},
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{JTAddr, Index})
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.addJumpTableIndex(JTI);
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auto JumpTableInst = MIB.buildInstr(AArch64::JumpTableDest32,
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{TargetReg, ScratchReg}, {JTAddr, Index})
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.addJumpTableIndex(JTI);
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// Build the indirect branch.
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MIB.buildInstr(AArch64::BR, {}, {TargetReg});
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I.eraseFromParent();
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return true;
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return constrainSelectedInstRegOperands(*JumpTableInst, TII, TRI, RBI);
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}
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bool AArch64InstructionSelector::selectJumpTable(
Lines changed: 61 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,61 @@
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -mtriple=aarch64-unknown-unknown -o - -verify-machineinstrs -run-pass=instruction-select %s | FileCheck %s
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# When we select the G_ZEXTLOAD, the SUBREG_TO_REG will initially land on a
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# gpr64sp register.
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#
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# This caused a test failure when selecting the G_BRJT, because it was not being
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# constrained. This test checks that the G_BRJT is actually being constrained.
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# As a result, the SUBREG_TO_REG should end up on a gpr64common.
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...
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---
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name: check_constrain
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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jumpTable:
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kind: block-address
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entries:
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- id: 0
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blocks: [ '%bb.4' ]
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body: |
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; CHECK-LABEL: name: check_constrain
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; CHECK: bb.0:
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; CHECK: successors: %bb.3(0x40000000), %bb.1(0x40000000)
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; CHECK: [[DEF:%[0-9]+]]:gpr64common = IMPLICIT_DEF
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; CHECK: [[LDRBBui:%[0-9]+]]:gpr32 = LDRBBui [[DEF]], 0 :: (load 1)
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; CHECK: [[SUBREG_TO_REG:%[0-9]+]]:gpr64common = SUBREG_TO_REG 0, [[LDRBBui]], %subreg.sub_32
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; CHECK: $xzr = SUBSXri [[SUBREG_TO_REG]], 8, 0, implicit-def $nzcv
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; CHECK: Bcc 8, %bb.3, implicit $nzcv
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; CHECK: bb.1:
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; CHECK: successors: %bb.2(0x40000000), %bb.3(0x40000000)
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; CHECK: [[MOVaddrJT:%[0-9]+]]:gpr64 = MOVaddrJT target-flags(aarch64-page) %jump-table.0, target-flags(aarch64-pageoff, aarch64-nc) %jump-table.0
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; CHECK: early-clobber %6:gpr64, early-clobber %7:gpr64sp = JumpTableDest32 [[MOVaddrJT]], [[SUBREG_TO_REG]], %jump-table.0
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; CHECK: BR %6
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; CHECK: bb.2:
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; CHECK: successors: %bb.3(0x80000000)
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; CHECK: B %bb.3
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; CHECK: bb.3:
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; CHECK: RET_ReallyLR
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bb.1:
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%1:gpr(p0) = G_IMPLICIT_DEF
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%5:gpr(s64) = G_ZEXTLOAD %1(p0) :: (load 1)
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%7:gpr(s64) = G_CONSTANT i64 8
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%16:gpr(s32) = G_ICMP intpred(ugt), %5(s64), %7
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%8:gpr(s1) = G_TRUNC %16(s32)
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G_BRCOND %8(s1), %bb.4
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bb.2:
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successors: %bb.3, %bb.4
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%9:gpr(p0) = G_JUMP_TABLE %jump-table.0
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G_BRJT %9(p0), %jump-table.0, %5(s64)
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bb.3:
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G_BR %bb.4
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bb.4:
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RET_ReallyLR
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...

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