[RISCV] Correct scheduling information for WriteVIRedMinMaxV in RISCVSchedSiFive7.td.

The 'let' with the Latency and Cycles from the previous defm should
apply to this one as well. Introduce a scope around the two defms.

Reviewed By: wangpc

Differential Revision: https://reviews.llvm.org/D159029

Author: topperc

llvm/lib/Target/RISCV/RISCVSchedSiFive7.td

@@ -774,11 +774,12 @@ foreach mx = SchedMxList in {
   foreach sew = SchedSEWSet<mx>.val in {
     defvar Cycles = SiFive7GetReductionCycles<mx, sew>.c;
     defvar IsWorstCase = SiFive7IsWorstCaseMXSEW<mx, sew, SchedMxList>.c;
-    let Latency = Cycles, ReleaseAtCycles = [Cycles] in
-    defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFive7VA],
-                                   mx, sew, IsWorstCase>;
-    defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFive7VA],
-                                   mx, sew, IsWorstCase>;
+    let Latency = Cycles, ReleaseAtCycles = [Cycles] in {
+      defm "" : LMULSEWWriteResMXSEW<"WriteVIRedV_From", [SiFive7VA],
+                                     mx, sew, IsWorstCase>;
+      defm "" : LMULSEWWriteResMXSEW<"WriteVIRedMinMaxV_From", [SiFive7VA],
+                                     mx, sew, IsWorstCase>;
+    }
   }
 }