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Commit 1634193

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Fix panic due to overflow in riscv.rs and int/shift.rs
1 parent b788cf3 commit 1634193

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2 files changed

+7
-7
lines changed

2 files changed

+7
-7
lines changed

src/int/shift.rs

+3-3
Original file line numberDiff line numberDiff line change
@@ -12,7 +12,7 @@ trait Ashl: DInt {
1212
} else {
1313
Self::from_lo_hi(
1414
self.lo().wrapping_shl(shl),
15-
self.lo().logical_shr(n_h - shl) | self.hi().wrapping_shl(shl),
15+
self.lo().logical_shr(n_h.wrapping_sub(shl)) | self.hi().wrapping_shl(shl),
1616
)
1717
}
1818
}
@@ -36,7 +36,7 @@ trait Ashr: DInt {
3636
self
3737
} else {
3838
Self::from_lo_hi(
39-
self.lo().logical_shr(shr) | self.hi().wrapping_shl(n_h - shr),
39+
self.lo().logical_shr(shr) | self.hi().wrapping_shl(n_h.wrapping_sub(shr)),
4040
self.hi().wrapping_shr(shr),
4141
)
4242
}
@@ -57,7 +57,7 @@ trait Lshr: DInt {
5757
self
5858
} else {
5959
Self::from_lo_hi(
60-
self.lo().logical_shr(shr) | self.hi().wrapping_shl(n_h - shr),
60+
self.lo().logical_shr(shr) | self.hi().wrapping_shl(n_h.wrapping_sub(shr)),
6161
self.hi().logical_shr(shr),
6262
)
6363
}

src/riscv.rs

+4-4
Original file line numberDiff line numberDiff line change
@@ -19,11 +19,11 @@ intrinsics! {
1919
// https://github.com/llvm/llvm-project/blob/main/compiler-rt/lib/builtins/riscv/int_mul_impl.inc
2020
pub extern "C" fn __mulsi3(a: u32, b: u32) -> u32 {
2121
let (mut a, mut b) = (a, b);
22-
let mut r = 0;
22+
let mut r: u32 = 0;
2323

2424
while a > 0 {
2525
if a & 1 > 0 {
26-
r += b;
26+
r = r.wrapping_add(b);
2727
}
2828
a >>= 1;
2929
b <<= 1;
@@ -35,11 +35,11 @@ intrinsics! {
3535
#[cfg(not(target_feature = "m"))]
3636
pub extern "C" fn __muldi3(a: u64, b: u64) -> u64 {
3737
let (mut a, mut b) = (a, b);
38-
let mut r = 0;
38+
let mut r: u64 = 0;
3939

4040
while a > 0 {
4141
if a & 1 > 0 {
42-
r += b;
42+
r = r.wrapping_add(b);
4343
}
4444
a >>= 1;
4545
b <<= 1;

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