@@ -2,7 +2,7 @@ use std::sync::atomic::{compiler_fence, fence, AtomicBool, AtomicIsize, AtomicU6
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fn main ( ) {
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atomic_bool ( ) ;
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- atomic_isize ( ) ;
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+ atomic_all_ops ( ) ;
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atomic_u64 ( ) ;
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atomic_fences ( ) ;
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weak_sometimes_fails ( ) ;
@@ -25,6 +25,7 @@ fn atomic_bool() {
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assert_eq ! ( * ATOMIC . get_mut( ) , false ) ;
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}
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}
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+
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// There isn't a trait to use to make this generic, so just use a macro
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macro_rules! compare_exchange_weak_loop {
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( $atom: expr, $from: expr, $to: expr, $succ_order: expr, $fail_order: expr) => {
@@ -39,10 +40,40 @@ macro_rules! compare_exchange_weak_loop {
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}
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} ;
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}
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- fn atomic_isize ( ) {
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+
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+ /// Make sure we can handle all the intrinsics
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+ fn atomic_all_ops ( ) {
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static ATOMIC : AtomicIsize = AtomicIsize :: new ( 0 ) ;
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+ static ATOMIC_UNSIGNED : AtomicU64 = AtomicU64 :: new ( 0 ) ;
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+
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+
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+ // loads
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+ for o in [ Relaxed , Acquire , SeqCst ] {
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+ ATOMIC . load ( o) ;
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+ }
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- // Make sure trans can emit all the intrinsics correctly
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+ // stores
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+ for o in [ Relaxed , Release , SeqCst ] {
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+ ATOMIC . store ( 1 , o) ;
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+ }
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+
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+ // most RMWs
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+ for o in [ Relaxed , Release , Acquire , AcqRel , SeqCst ] {
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+ ATOMIC . swap ( 0 , o) ;
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+ ATOMIC . fetch_or ( 0 , o) ;
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+ ATOMIC . fetch_xor ( 0 , o) ;
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+ ATOMIC . fetch_and ( 0 , o) ;
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+ ATOMIC . fetch_nand ( 0 , o) ;
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+ ATOMIC . fetch_add ( 0 , o) ;
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+ ATOMIC . fetch_sub ( 0 , o) ;
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+ ATOMIC . fetch_min ( 0 , o) ;
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+ ATOMIC . fetch_max ( 0 , o) ;
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+ ATOMIC_UNSIGNED . fetch_min ( 0 , o) ;
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+ ATOMIC_UNSIGNED . fetch_max ( 0 , o) ;
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+ }
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+
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+ // RMWs with deparate failure ordering
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+ ATOMIC . store ( 0 , SeqCst ) ;
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assert_eq ! ( ATOMIC . compare_exchange( 0 , 1 , Relaxed , Relaxed ) , Ok ( 0 ) ) ;
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assert_eq ! ( ATOMIC . compare_exchange( 0 , 2 , Acquire , Relaxed ) , Err ( 1 ) ) ;
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assert_eq ! ( ATOMIC . compare_exchange( 0 , 1 , Release , Relaxed ) , Err ( 1 ) ) ;
@@ -59,7 +90,6 @@ fn atomic_isize() {
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assert_eq ! ( ATOMIC . compare_exchange_weak( 0 , 1 , Release , Relaxed ) , Err ( 1 ) ) ;
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compare_exchange_weak_loop ! ( ATOMIC , 1 , 0 , AcqRel , Relaxed ) ;
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assert_eq ! ( ATOMIC . load( Relaxed ) , 0 ) ;
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- ATOMIC . compare_exchange_weak ( 0 , 1 , AcqRel , Relaxed ) . ok ( ) ;
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ATOMIC . compare_exchange_weak ( 0 , 1 , SeqCst , Relaxed ) . ok ( ) ;
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ATOMIC . compare_exchange_weak ( 0 , 1 , Acquire , Acquire ) . ok ( ) ;
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ATOMIC . compare_exchange_weak ( 0 , 1 , AcqRel , Acquire ) . ok ( ) ;
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