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1 parent 910674f commit e300847Copy full SHA for e300847
tests/codegen/simd/simd-wide-sum.rs
@@ -52,6 +52,8 @@ pub fn wider_reduce_iter(x: Simd<u8, N>) -> u16 {
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#[no_mangle]
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// CHECK-LABEL: @wider_reduce_into_iter
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pub fn wider_reduce_into_iter(x: Simd<u8, N>) -> u16 {
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+ // FIXME: It would be nice if this was exactly the same as the above tests,
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+ // but at the time of writing this comment, that didn't happen on LLVM main.
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// CHECK: call i16 @llvm.vector.reduce.add
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x.to_array().into_iter().map(u16::from).sum()
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}
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