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Stabilize Arm64EC inline assembly
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‎compiler/rustc_ast_lowering/src/asm.rs

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@@ -45,6 +45,7 @@ impl<'a, 'hir> LoweringContext<'a, 'hir> {
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| asm::InlineAsmArch::X86_64
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| asm::InlineAsmArch::Arm
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| asm::InlineAsmArch::AArch64
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| asm::InlineAsmArch::Arm64EC
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| asm::InlineAsmArch::RiscV32
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| asm::InlineAsmArch::RiscV64
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| asm::InlineAsmArch::LoongArch64

‎src/doc/unstable-book/src/language-features/asm-experimental-arch.md

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@@ -18,7 +18,6 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
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- MSP430
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- M68k
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- CSKY
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- Arm64EC
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- SPARC
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## Register classes
@@ -53,9 +52,6 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
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| CSKY | `freg` | `f[0-31]` | `f` |
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| SPARC | `reg` | `r[2-29]` | `r` |
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| SPARC | `yreg` | `y` | Only clobbers |
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| Arm64EC | `reg` | `x[0-12]`, `x[15-22]`, `x[25-27]`, `x30` | `r` |
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| Arm64EC | `vreg` | `v[0-15]` | `w` |
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| Arm64EC | `vreg_low16` | `v[0-15]` | `x` |
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> **Notes**:
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> - NVPTX doesn't have a fixed register set, so named registers are not supported.
@@ -92,8 +88,6 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
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| CSKY | `freg` | None | `f32`, |
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| SPARC | `reg` | None | `i8`, `i16`, `i32`, `i64` (SPARC64 only) |
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| SPARC | `yreg` | N/A | Only clobbers |
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| Arm64EC | `reg` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64` |
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| Arm64EC | `vreg` | None | `i8`, `i16`, `i32`, `f32`, `i64`, `f64`, <br> `i8x8`, `i16x4`, `i32x2`, `i64x1`, `f32x2`, `f64x1`, <br> `i8x16`, `i16x8`, `i32x4`, `i64x2`, `f32x4`, `f64x2` |
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## Register aliases
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@@ -134,12 +128,6 @@ This feature tracks `asm!` and `global_asm!` support for the following architect
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| SPARC | `r[8-15]` | `o[0-7]` |
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| SPARC | `r[16-23]` | `l[0-7]` |
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| SPARC | `r[24-31]` | `i[0-7]` |
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| Arm64EC | `x[0-30]` | `w[0-30]` |
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| Arm64EC | `x29` | `fp` |
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| Arm64EC | `x30` | `lr` |
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| Arm64EC | `sp` | `wsp` |
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| Arm64EC | `xzr` | `wzr` |
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| Arm64EC | `v[0-15]` | `b[0-15]`, `h[0-15]`, `s[0-15]`, `d[0-15]`, `q[0-15]` |
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> **Notes**:
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> - TI does not mandate a frame pointer for MSP430, but toolchains are allowed
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| Architecture | Unsupported register | Reason |
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| ------------ | --------------------------------------- | ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- |
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| All | `sp`, `r14`/`o6` (SPARC) | The stack pointer must be restored to its original value at the end of an asm code block. |
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| All | `fr` (Hexagon), `fp` (PowerPC), `$fp` (MIPS), `Y` (AVR), `r4` (MSP430), `a6` (M68k), `r30`/`i6` (SPARC), `x29` (Arm64EC) | The frame pointer cannot be used as an input or output. |
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| All | `r19` (Hexagon), `r29` (PowerPC), `r30` (PowerPC), `x19` (Arm64EC) | These are used internally by LLVM as "base pointer" for functions with complex stack frames. |
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| All | `fr` (Hexagon), `fp` (PowerPC), `$fp` (MIPS), `Y` (AVR), `r4` (MSP430), `a6` (M68k), `r30`/`i6` (SPARC) | The frame pointer cannot be used as an input or output. |
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| All | `r19` (Hexagon), `r29` (PowerPC), `r30` (PowerPC) | These are used internally by LLVM as "base pointer" for functions with complex stack frames. |
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| MIPS | `$0` or `$zero` | This is a constant zero register which can't be modified. |
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| MIPS | `$1` or `$at` | Reserved for assembler. |
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| MIPS | `$26`/`$k0`, `$27`/`$k1` | OS-reserved registers. |
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| SPARC | `r5`/`g5` | Reserved for system. (SPARC32 only) |
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| SPARC | `r6`/`g6`, `r7`/`g7` | Reserved for system. |
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| SPARC | `r31`/`i7` | Return address cannot be used as inputs or outputs. |
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| Arm64EC | `xzr` | This is a constant zero register which can't be modified. |
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| Arm64EC | `x18` | This is an OS-reserved register. |
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| Arm64EC | `x13`, `x14`, `x23`, `x24`, `x28`, `v[16-31]` | These are AArch64 registers that are not supported for Arm64EC. |
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## Template modifiers
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| SPARC | `reg` | None | `%o0` | None |
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| CSKY | `reg` | None | `r0` | None |
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| CSKY | `freg` | None | `f0` | None |
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| Arm64EC | `reg` | None | `x0` | `x` |
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| Arm64EC | `reg` | `w` | `w0` | `w` |
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| Arm64EC | `reg` | `x` | `x0` | `x` |
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| Arm64EC | `vreg` | None | `v0` | None |
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| Arm64EC | `vreg` | `v` | `v0` | None |
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| Arm64EC | `vreg` | `b` | `b0` | `b` |
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| Arm64EC | `vreg` | `h` | `h0` | `h` |
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| Arm64EC | `vreg` | `s` | `s0` | `s` |
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| Arm64EC | `vreg` | `d` | `d0` | `d` |
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| Arm64EC | `vreg` | `q` | `q0` | `q` |
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# Flags covered by `preserves_flags`
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- SPARC
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- Integer condition codes (`icc` and `xcc`)
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- Floating-point condition codes (`fcc[0-3]`)
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- Arm64EC
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- Condition flags (`NZCV` register).
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- Floating-point status (`FPSR` register).

‎tests/assembly/asm/aarch64-types.rs

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//@ [arm64ec] needs-llvm-components: aarch64
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//@ compile-flags: -Zmerge-functions=disabled
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#![feature(no_core, lang_items, rustc_attrs, repr_simd, asm_experimental_arch, f16, f128)]
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#![feature(no_core, lang_items, rustc_attrs, repr_simd, f16, f128)]
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#![crate_type = "rlib"]
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#![no_core]
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#![allow(asm_sub_register, non_camel_case_types)]

‎tests/codegen/asm/arm64ec-clobbers.rs

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//@ needs-llvm-components: aarch64
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#![crate_type = "rlib"]
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#![feature(no_core, rustc_attrs, lang_items, asm_experimental_arch)]
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#![feature(no_core, rustc_attrs, lang_items)]
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#![no_core]
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#[lang = "sized"]

‎tests/ui/asm/aarch64/arm64ec-sve.rs

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//@ needs-llvm-components: aarch64
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#![crate_type = "rlib"]
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#![feature(no_core, rustc_attrs, lang_items, asm_experimental_arch)]
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#![feature(no_core, rustc_attrs, lang_items)]
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#![no_core]
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// SVE cannot be used for Arm64EC

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