Skip to content
This repository was archived by the owner on May 28, 2025. It is now read-only.

Commit 4f5133a

Browse files
gchateletgchatelet
committed
[Alignment][NFC] Migrate AArch64, ARM, Hexagon, MSP and NVPTX backends to Align
This patch is part of a series to introduce an Alignment type. See this thread for context: http://lists.llvm.org/pipermail/llvm-dev/2019-July/133851.html See this patch for the introduction of the type: https://reviews.llvm.org/D64790 Differential Revision: https://reviews.llvm.org/D82749
1 parent ed4328c commit 4f5133a

File tree

8 files changed

+66
-66
lines changed

8 files changed

+66
-66
lines changed

‎llvm/lib/Target/AArch64/AArch64FrameLowering.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2519,8 +2519,8 @@ void AArch64FrameLowering::determineCalleeSaves(MachineFunction &MF,
25192519
const TargetRegisterInfo *TRI = MF.getSubtarget().getRegisterInfo();
25202520
const TargetRegisterClass &RC = AArch64::GPR64RegClass;
25212521
unsigned Size = TRI->getSpillSize(RC);
2522-
unsigned Align = TRI->getSpillAlignment(RC);
2523-
int FI = MFI.CreateStackObject(Size, Align, false);
2522+
Align Alignment = TRI->getSpillAlign(RC);
2523+
int FI = MFI.CreateStackObject(Size, Alignment, false);
25242524
RS->addScavengingFrameIndex(FI);
25252525
LLVM_DEBUG(dbgs() << "No available CS registers, allocated fi#" << FI
25262526
<< " as the emergency spill slot.\n");

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 12 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -3318,9 +3318,9 @@ SDValue AArch64TargetLowering::LowerSTORE(SDValue Op,
33183318
return LowerFixedLengthVectorStoreToSVE(Op, DAG);
33193319

33203320
unsigned AS = StoreNode->getAddressSpace();
3321-
unsigned Align = StoreNode->getAlignment();
3322-
if (Align < MemVT.getStoreSize() &&
3323-
!allowsMisalignedMemoryAccesses(MemVT, AS, Align,
3321+
Align Alignment = StoreNode->getAlign();
3322+
if (Alignment < MemVT.getStoreSize() &&
3323+
!allowsMisalignedMemoryAccesses(MemVT, AS, Alignment.value(),
33243324
StoreNode->getMemOperand()->getFlags(),
33253325
nullptr)) {
33263326
return scalarizeVectorStore(StoreNode, DAG);
@@ -4427,9 +4427,9 @@ AArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
44274427
"Only scalable vectors can be passed indirectly");
44284428
MachineFrameInfo &MFI = DAG.getMachineFunction().getFrameInfo();
44294429
Type *Ty = EVT(VA.getValVT()).getTypeForEVT(*DAG.getContext());
4430-
unsigned Align = DAG.getDataLayout().getPrefTypeAlignment(Ty);
4430+
Align Alignment = DAG.getDataLayout().getPrefTypeAlign(Ty);
44314431
int FI = MFI.CreateStackObject(
4432-
VA.getValVT().getStoreSize().getKnownMinSize(), Align, false);
4432+
VA.getValVT().getStoreSize().getKnownMinSize(), Alignment, false);
44334433
MFI.setStackID(FI, TargetStackID::SVEVector);
44344434

44354435
SDValue SpillSlot = DAG.getFrameIndex(
@@ -6095,7 +6095,7 @@ SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
60956095
SDLoc DL(Op);
60966096
SDValue Chain = Op.getOperand(0);
60976097
SDValue Addr = Op.getOperand(1);
6098-
unsigned Align = Op.getConstantOperandVal(3);
6098+
MaybeAlign Align(Op.getConstantOperandVal(3));
60996099
unsigned MinSlotSize = Subtarget->isTargetILP32() ? 4 : 8;
61006100
auto PtrVT = getPointerTy(DAG.getDataLayout());
61016101
auto PtrMemVT = getPointerMemTy(DAG.getDataLayout());
@@ -6104,12 +6104,11 @@ SDValue AArch64TargetLowering::LowerVAARG(SDValue Op, SelectionDAG &DAG) const {
61046104
Chain = VAList.getValue(1);
61056105
VAList = DAG.getZExtOrTrunc(VAList, DL, PtrVT);
61066106

6107-
if (Align > MinSlotSize) {
6108-
assert(((Align & (Align - 1)) == 0) && "Expected Align to be a power of 2");
6107+
if (Align && *Align > MinSlotSize) {
61096108
VAList = DAG.getNode(ISD::ADD, DL, PtrVT, VAList,
6110-
DAG.getConstant(Align - 1, DL, PtrVT));
6109+
DAG.getConstant(Align->value() - 1, DL, PtrVT));
61116110
VAList = DAG.getNode(ISD::AND, DL, PtrVT, VAList,
6112-
DAG.getConstant(-(int64_t)Align, DL, PtrVT));
6111+
DAG.getConstant(-(int64_t)Align->value(), DL, PtrVT));
61136112
}
61146113

61156114
Type *ArgTy = VT.getTypeForEVT(*DAG.getContext());
@@ -9110,7 +9109,7 @@ AArch64TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
91109109
SDNode *Node = Op.getNode();
91119110
SDValue Chain = Op.getOperand(0);
91129111
SDValue Size = Op.getOperand(1);
9113-
unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
9112+
MaybeAlign Align(cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
91149113
EVT VT = Node->getValueType(0);
91159114

91169115
if (DAG.getMachineFunction().getFunction().hasFnAttribute(
@@ -9120,7 +9119,7 @@ AArch64TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
91209119
SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size);
91219120
if (Align)
91229121
SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
9123-
DAG.getConstant(-(uint64_t)Align, dl, VT));
9122+
DAG.getConstant(-(uint64_t)Align->value(), dl, VT));
91249123
Chain = DAG.getCopyToReg(Chain, dl, AArch64::SP, SP);
91259124
SDValue Ops[2] = {SP, Chain};
91269125
return DAG.getMergeValues(Ops, dl);
@@ -9135,7 +9134,7 @@ AArch64TargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op,
91359134
SP = DAG.getNode(ISD::SUB, dl, MVT::i64, SP, Size);
91369135
if (Align)
91379136
SP = DAG.getNode(ISD::AND, dl, VT, SP.getValue(0),
9138-
DAG.getConstant(-(uint64_t)Align, dl, VT));
9137+
DAG.getConstant(-(uint64_t)Align->value(), dl, VT));
91399138
Chain = DAG.getCopyToReg(Chain, dl, AArch64::SP, SP);
91409139

91419140
Chain = DAG.getCALLSEQ_END(Chain, DAG.getIntPtrConstant(0, dl, true),

‎llvm/lib/Target/ARM/ARMFrameLowering.cpp

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -2144,8 +2144,9 @@ void ARMFrameLowering::determineCalleeSaves(MachineFunction &MF,
21442144
LLVM_DEBUG(dbgs() << "Reserving emergency spill slot\n");
21452145
const TargetRegisterClass &RC = ARM::GPRRegClass;
21462146
unsigned Size = TRI->getSpillSize(RC);
2147-
unsigned Align = TRI->getSpillAlignment(RC);
2148-
RS->addScavengingFrameIndex(MFI.CreateStackObject(Size, Align, false));
2147+
Align Alignment = TRI->getSpillAlign(RC);
2148+
RS->addScavengingFrameIndex(
2149+
MFI.CreateStackObject(Size, Alignment, false));
21492150
}
21502151
}
21512152
}

‎llvm/lib/Target/ARM/ARMISelDAGToDAG.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -1726,7 +1726,7 @@ bool ARMDAGToDAGISel::tryMVEIndexedLoad(SDNode *N) {
17261726
EVT LoadedVT;
17271727
unsigned Opcode = 0;
17281728
bool isSExtLd, isPre;
1729-
unsigned Align;
1729+
Align Alignment;
17301730
ARMVCC::VPTCodes Pred;
17311731
SDValue PredReg;
17321732
SDValue Chain, Base, Offset;
@@ -1742,7 +1742,7 @@ bool ARMDAGToDAGISel::tryMVEIndexedLoad(SDNode *N) {
17421742
Chain = LD->getChain();
17431743
Base = LD->getBasePtr();
17441744
Offset = LD->getOffset();
1745-
Align = LD->getAlignment();
1745+
Alignment = LD->getAlign();
17461746
isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
17471747
isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
17481748
Pred = ARMVCC::None;
@@ -1758,7 +1758,7 @@ bool ARMDAGToDAGISel::tryMVEIndexedLoad(SDNode *N) {
17581758
Chain = LD->getChain();
17591759
Base = LD->getBasePtr();
17601760
Offset = LD->getOffset();
1761-
Align = LD->getAlignment();
1761+
Alignment = LD->getAlign();
17621762
isSExtLd = LD->getExtensionType() == ISD::SEXTLOAD;
17631763
isPre = (AM == ISD::PRE_INC) || (AM == ISD::PRE_DEC);
17641764
Pred = ARMVCC::Then;
@@ -1772,7 +1772,7 @@ bool ARMDAGToDAGISel::tryMVEIndexedLoad(SDNode *N) {
17721772
bool CanChangeType = Subtarget->isLittle() && !isa<MaskedLoadSDNode>(N);
17731773

17741774
SDValue NewOffset;
1775-
if (Align >= 2 && LoadedVT == MVT::v4i16 &&
1775+
if (Alignment >= Align(2) && LoadedVT == MVT::v4i16 &&
17761776
SelectT2AddrModeImm7Offset(N, Offset, NewOffset, 1)) {
17771777
if (isSExtLd)
17781778
Opcode = isPre ? ARM::MVE_VLDRHS32_pre : ARM::MVE_VLDRHS32_post;
@@ -1790,12 +1790,12 @@ bool ARMDAGToDAGISel::tryMVEIndexedLoad(SDNode *N) {
17901790
Opcode = isPre ? ARM::MVE_VLDRBS32_pre : ARM::MVE_VLDRBS32_post;
17911791
else
17921792
Opcode = isPre ? ARM::MVE_VLDRBU32_pre : ARM::MVE_VLDRBU32_post;
1793-
} else if (Align >= 4 &&
1793+
} else if (Alignment >= Align(4) &&
17941794
(CanChangeType || LoadedVT == MVT::v4i32 ||
17951795
LoadedVT == MVT::v4f32) &&
17961796
SelectT2AddrModeImm7Offset(N, Offset, NewOffset, 2))
17971797
Opcode = isPre ? ARM::MVE_VLDRWU32_pre : ARM::MVE_VLDRWU32_post;
1798-
else if (Align >= 2 &&
1798+
else if (Alignment >= Align(2) &&
17991799
(CanChangeType || LoadedVT == MVT::v8i16 ||
18001800
LoadedVT == MVT::v8f16) &&
18011801
SelectT2AddrModeImm7Offset(N, Offset, NewOffset, 1))

‎llvm/lib/Target/ARM/ARMISelLowering.cpp

Lines changed: 22 additions & 21 deletions
Original file line numberDiff line numberDiff line change
@@ -16827,7 +16827,7 @@ static bool getT2IndexedAddressParts(SDNode *Ptr, EVT VT,
1682716827
return false;
1682816828
}
1682916829

16830-
static bool getMVEIndexedAddressParts(SDNode *Ptr, EVT VT, unsigned Align,
16830+
static bool getMVEIndexedAddressParts(SDNode *Ptr, EVT VT, Align Alignment,
1683116831
bool isSEXTLoad, bool IsMasked, bool isLE,
1683216832
SDValue &Base, SDValue &Offset,
1683316833
bool &isInc, SelectionDAG &DAG) {
@@ -16862,16 +16862,16 @@ static bool getMVEIndexedAddressParts(SDNode *Ptr, EVT VT, unsigned Align,
1686216862
// (in BE/masked) type.
1686316863
Base = Ptr->getOperand(0);
1686416864
if (VT == MVT::v4i16) {
16865-
if (Align >= 2 && IsInRange(RHSC, 0x80, 2))
16865+
if (Alignment >= 2 && IsInRange(RHSC, 0x80, 2))
1686616866
return true;
1686716867
} else if (VT == MVT::v4i8 || VT == MVT::v8i8) {
1686816868
if (IsInRange(RHSC, 0x80, 1))
1686916869
return true;
16870-
} else if (Align >= 4 &&
16870+
} else if (Alignment >= 4 &&
1687116871
(CanChangeType || VT == MVT::v4i32 || VT == MVT::v4f32) &&
1687216872
IsInRange(RHSC, 0x80, 4))
1687316873
return true;
16874-
else if (Align >= 2 &&
16874+
else if (Alignment >= 2 &&
1687516875
(CanChangeType || VT == MVT::v8i16 || VT == MVT::v8f16) &&
1687616876
IsInRange(RHSC, 0x80, 2))
1687716877
return true;
@@ -16893,28 +16893,28 @@ ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1689316893

1689416894
EVT VT;
1689516895
SDValue Ptr;
16896-
unsigned Align;
16896+
Align Alignment;
1689716897
bool isSEXTLoad = false;
1689816898
bool IsMasked = false;
1689916899
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1690016900
Ptr = LD->getBasePtr();
1690116901
VT = LD->getMemoryVT();
16902-
Align = LD->getAlignment();
16902+
Alignment = LD->getAlign();
1690316903
isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1690416904
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1690516905
Ptr = ST->getBasePtr();
1690616906
VT = ST->getMemoryVT();
16907-
Align = ST->getAlignment();
16907+
Alignment = ST->getAlign();
1690816908
} else if (MaskedLoadSDNode *LD = dyn_cast<MaskedLoadSDNode>(N)) {
1690916909
Ptr = LD->getBasePtr();
1691016910
VT = LD->getMemoryVT();
16911-
Align = LD->getAlignment();
16911+
Alignment = LD->getAlign();
1691216912
isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1691316913
IsMasked = true;
1691416914
} else if (MaskedStoreSDNode *ST = dyn_cast<MaskedStoreSDNode>(N)) {
1691516915
Ptr = ST->getBasePtr();
1691616916
VT = ST->getMemoryVT();
16917-
Align = ST->getAlignment();
16917+
Alignment = ST->getAlign();
1691816918
IsMasked = true;
1691916919
} else
1692016920
return false;
@@ -16923,9 +16923,9 @@ ARMTargetLowering::getPreIndexedAddressParts(SDNode *N, SDValue &Base,
1692316923
bool isLegal = false;
1692416924
if (VT.isVector())
1692516925
isLegal = Subtarget->hasMVEIntegerOps() &&
16926-
getMVEIndexedAddressParts(Ptr.getNode(), VT, Align, isSEXTLoad,
16927-
IsMasked, Subtarget->isLittle(), Base,
16928-
Offset, isInc, DAG);
16926+
getMVEIndexedAddressParts(
16927+
Ptr.getNode(), VT, Alignment, isSEXTLoad, IsMasked,
16928+
Subtarget->isLittle(), Base, Offset, isInc, DAG);
1692916929
else {
1693016930
if (Subtarget->isThumb2())
1693116931
isLegal = getT2IndexedAddressParts(Ptr.getNode(), VT, isSEXTLoad, Base,
@@ -16951,31 +16951,31 @@ bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1695116951
SelectionDAG &DAG) const {
1695216952
EVT VT;
1695316953
SDValue Ptr;
16954-
unsigned Align;
16954+
Align Alignment;
1695516955
bool isSEXTLoad = false, isNonExt;
1695616956
bool IsMasked = false;
1695716957
if (LoadSDNode *LD = dyn_cast<LoadSDNode>(N)) {
1695816958
VT = LD->getMemoryVT();
1695916959
Ptr = LD->getBasePtr();
16960-
Align = LD->getAlignment();
16960+
Alignment = LD->getAlign();
1696116961
isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1696216962
isNonExt = LD->getExtensionType() == ISD::NON_EXTLOAD;
1696316963
} else if (StoreSDNode *ST = dyn_cast<StoreSDNode>(N)) {
1696416964
VT = ST->getMemoryVT();
1696516965
Ptr = ST->getBasePtr();
16966-
Align = ST->getAlignment();
16966+
Alignment = ST->getAlign();
1696716967
isNonExt = !ST->isTruncatingStore();
1696816968
} else if (MaskedLoadSDNode *LD = dyn_cast<MaskedLoadSDNode>(N)) {
1696916969
VT = LD->getMemoryVT();
1697016970
Ptr = LD->getBasePtr();
16971-
Align = LD->getAlignment();
16971+
Alignment = LD->getAlign();
1697216972
isSEXTLoad = LD->getExtensionType() == ISD::SEXTLOAD;
1697316973
isNonExt = LD->getExtensionType() == ISD::NON_EXTLOAD;
1697416974
IsMasked = true;
1697516975
} else if (MaskedStoreSDNode *ST = dyn_cast<MaskedStoreSDNode>(N)) {
1697616976
VT = ST->getMemoryVT();
1697716977
Ptr = ST->getBasePtr();
16978-
Align = ST->getAlignment();
16978+
Alignment = ST->getAlign();
1697916979
isNonExt = !ST->isTruncatingStore();
1698016980
IsMasked = true;
1698116981
} else
@@ -17001,7 +17001,7 @@ bool ARMTargetLowering::getPostIndexedAddressParts(SDNode *N, SDNode *Op,
1700117001
bool isLegal = false;
1700217002
if (VT.isVector())
1700317003
isLegal = Subtarget->hasMVEIntegerOps() &&
17004-
getMVEIndexedAddressParts(Op, VT, Align, isSEXTLoad, IsMasked,
17004+
getMVEIndexedAddressParts(Op, VT, Alignment, isSEXTLoad, IsMasked,
1700517005
Subtarget->isLittle(), Base, Offset,
1700617006
isInc, DAG);
1700717007
else {
@@ -17758,13 +17758,14 @@ ARMTargetLowering::LowerDYNAMIC_STACKALLOC(SDValue Op, SelectionDAG &DAG) const
1775817758

1775917759
if (DAG.getMachineFunction().getFunction().hasFnAttribute(
1776017760
"no-stack-arg-probe")) {
17761-
unsigned Align = cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue();
17761+
MaybeAlign Align(cast<ConstantSDNode>(Op.getOperand(2))->getZExtValue());
1776217762
SDValue SP = DAG.getCopyFromReg(Chain, DL, ARM::SP, MVT::i32);
1776317763
Chain = SP.getValue(1);
1776417764
SP = DAG.getNode(ISD::SUB, DL, MVT::i32, SP, Size);
1776517765
if (Align)
17766-
SP = DAG.getNode(ISD::AND, DL, MVT::i32, SP.getValue(0),
17767-
DAG.getConstant(-(uint64_t)Align, DL, MVT::i32));
17766+
SP =
17767+
DAG.getNode(ISD::AND, DL, MVT::i32, SP.getValue(0),
17768+
DAG.getConstant(-(uint64_t)Align->value(), DL, MVT::i32));
1776817769
Chain = DAG.getCopyToReg(Chain, DL, ARM::SP, SP);
1776917770
SDValue Ops[2] = { SP, Chain };
1777017771
return DAG.getMergeValues(Ops, DL);

‎llvm/lib/Target/Hexagon/HexagonVExtract.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -107,7 +107,7 @@ bool HexagonVExtract::runOnMachineFunction(MachineFunction &MF) {
107107
Register AR =
108108
MF.getInfo<HexagonMachineFunctionInfo>()->getStackAlignBaseVReg();
109109
std::map<unsigned, SmallVector<MachineInstr*,4>> VExtractMap;
110-
unsigned MaxAlign = 0;
110+
MaybeAlign MaxAlign;
111111
bool Changed = false;
112112

113113
for (MachineBasicBlock &MBB : MF) {
@@ -137,14 +137,14 @@ bool HexagonVExtract::runOnMachineFunction(MachineFunction &MF) {
137137
continue;
138138

139139
const auto &VecRC = *MRI.getRegClass(VecR);
140-
unsigned Align = HRI.getSpillAlignment(VecRC);
141-
MaxAlign = std::max(MaxAlign, Align);
140+
Align Alignment = HRI.getSpillAlign(VecRC);
141+
MaxAlign = max(MaxAlign, Alignment);
142142
// Make sure this is not a spill slot: spill slots cannot be aligned
143143
// if there are variable-sized objects on the stack. They must be
144144
// accessible via FP (which is not aligned), because SP is unknown,
145145
// and AP may not be available at the location of the load/store.
146-
int FI = MFI.CreateStackObject(HRI.getSpillSize(VecRC), Align,
147-
/*isSpillSlot*/false);
146+
int FI = MFI.CreateStackObject(HRI.getSpillSize(VecRC), Alignment,
147+
/*isSpillSlot*/ false);
148148

149149
MachineInstr *DefI = MRI.getVRegDef(VecR);
150150
MachineBasicBlock::iterator At = std::next(DefI->getIterator());
@@ -178,13 +178,13 @@ bool HexagonVExtract::runOnMachineFunction(MachineFunction &MF) {
178178
}
179179
}
180180

181-
if (AR) {
181+
if (AR && MaxAlign) {
182182
// Update the required stack alignment.
183183
MachineInstr *AlignaI = MRI.getVRegDef(AR);
184184
assert(AlignaI->getOpcode() == Hexagon::PS_aligna);
185185
MachineOperand &Op = AlignaI->getOperand(1);
186-
if (MaxAlign > Op.getImm())
187-
Op.setImm(MaxAlign);
186+
if (*MaxAlign > Op.getImm())
187+
Op.setImm(MaxAlign->value());
188188
}
189189

190190
return Changed;

‎llvm/lib/Target/MSP430/MSP430ISelDAGToDAG.cpp

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -50,7 +50,7 @@ namespace {
5050
const BlockAddress *BlockAddr = nullptr;
5151
const char *ES = nullptr;
5252
int JT = -1;
53-
unsigned Align = 0; // CP alignment.
53+
Align Alignment; // CP alignment.
5454

5555
MSP430ISelAddressMode() = default;
5656

@@ -74,12 +74,12 @@ namespace {
7474
} else if (CP) {
7575
errs() << " CP ";
7676
CP->dump();
77-
errs() << " Align" << Align << '\n';
77+
errs() << " Align" << Alignment.value() << '\n';
7878
} else if (ES) {
7979
errs() << "ES ";
8080
errs() << ES << '\n';
8181
} else if (JT != -1)
82-
errs() << " JT" << JT << " Align" << Align << '\n';
82+
errs() << " JT" << JT << " Align" << Alignment.value() << '\n';
8383
}
8484
#endif
8585
};
@@ -146,7 +146,7 @@ bool MSP430DAGToDAGISel::MatchWrapper(SDValue N, MSP430ISelAddressMode &AM) {
146146
//AM.SymbolFlags = G->getTargetFlags();
147147
} else if (ConstantPoolSDNode *CP = dyn_cast<ConstantPoolSDNode>(N0)) {
148148
AM.CP = CP->getConstVal();
149-
AM.Align = CP->getAlign().value();
149+
AM.Alignment = CP->getAlign();
150150
AM.Disp += CP->getOffset();
151151
//AM.SymbolFlags = CP->getTargetFlags();
152152
} else if (ExternalSymbolSDNode *S = dyn_cast<ExternalSymbolSDNode>(N0)) {
@@ -263,8 +263,8 @@ bool MSP430DAGToDAGISel::SelectAddr(SDValue N,
263263
MVT::i16, AM.Disp,
264264
0/*AM.SymbolFlags*/);
265265
else if (AM.CP)
266-
Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16, Align(AM.Align),
267-
AM.Disp, 0 /*AM.SymbolFlags*/);
266+
Disp = CurDAG->getTargetConstantPool(AM.CP, MVT::i16, AM.Alignment, AM.Disp,
267+
0 /*AM.SymbolFlags*/);
268268
else if (AM.ES)
269269
Disp = CurDAG->getTargetExternalSymbol(AM.ES, MVT::i16, 0/*AM.SymbolFlags*/);
270270
else if (AM.JT != -1)

0 commit comments

Comments
 (0)