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Merge #470
470: Use xtensa-lx r=therealprof a=MabezDev The xtensa runtime and device crates have been merged into a single device and runtime crate, feature gating the CPU features. * s/XtensaLX6/XtensaLX/g * s/"xtensalx6"/"xtensa-lx"/g * Replaces lx6 with the generic lx crate * Updates the CI script accordingly Co-authored-by: Scott Mabin <[email protected]>
2 parents d6b0e77 + d61c380 commit 72ec77f

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+20
-18
lines changed

8 files changed

+20
-18
lines changed

ci/script.sh

Lines changed: 7 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -694,13 +694,15 @@ main() {
694694
echo '[dependencies.bare-metal]' >> $td/Cargo.toml
695695
echo 'version = "0.2.0"' >> $td/Cargo.toml
696696

697-
echo '[dependencies.xtensa-lx6]' >> $td/Cargo.toml
698-
echo 'version = "0.1.0"' >> $td/Cargo.toml
697+
echo '[dependencies.xtensa-lx]' >> $td/Cargo.toml
698+
echo 'version = "0.3.0"' >> $td/Cargo.toml
699+
echo 'features = ["lx6"]' >> $td/Cargo.toml
699700

700-
echo '[dependencies.xtensa-lx6-rt]' >> $td/Cargo.toml
701-
echo 'version = "0.2.0"' >> $td/Cargo.toml
701+
echo '[dependencies.xtensa-lx-rt]' >> $td/Cargo.toml
702+
echo 'version = "0.5.0"' >> $td/Cargo.toml
703+
echo 'features = ["lx6"]' >> $td/Cargo.toml
702704

703-
test_svd_for_target xtensalx6 https://raw.githubusercontent.com/arjanmels/esp32/add-output-svd/svd/esp32.svd
705+
test_svd_for_target xtensa-lx https://raw.githubusercontent.com/esp-rs/esp32/master/svd/esp32.svd
704706
;;
705707

706708
esac

ci/svd2rust-regress/src/svd_test.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -134,7 +134,7 @@ pub fn test(
134134
CortexM => CRATES_CORTEX_M.iter(),
135135
RiscV => CRATES_RISCV.iter(),
136136
Msp430 => CRATES_MSP430.iter(),
137-
XtensaLX6 => CRATES_XTENSALX6.iter(),
137+
XtensaLX => CRATES_XTENSALX6.iter(),
138138
})
139139
.chain(PROFILE_ALL.iter())
140140
.chain(FEATURES_ALL.iter())
@@ -167,7 +167,7 @@ pub fn test(
167167
CortexM => "cortex-m",
168168
Msp430 => "msp430",
169169
RiscV => "riscv",
170-
XtensaLX6 => "xtensalx6",
170+
XtensaLX => "xtensa-lx",
171171
};
172172
let mut svd2rust_bin = Command::new(bin_path);
173173
if nightly {
@@ -184,14 +184,14 @@ pub fn test(
184184
true,
185185
"svd2rust",
186186
Some(&lib_rs_file)
187-
.filter(|_| (t.arch != CortexM) && (t.arch != Msp430) && (t.arch != XtensaLX6)),
187+
.filter(|_| (t.arch != CortexM) && (t.arch != Msp430) && (t.arch != XtensaLX)),
188188
Some(&svd2rust_err_file),
189189
&[],
190190
)?;
191191
process_stderr_paths.push(svd2rust_err_file);
192192

193193
match t.arch {
194-
CortexM | Msp430 | XtensaLX6 => {
194+
CortexM | Msp430 | XtensaLX => {
195195
// TODO: Give error the path to stderr
196196
fs::rename(path_helper_base(&chip_dir, &["lib.rs"]), &lib_rs_file)
197197
.chain_err(|| "While moving lib.rs file")?

ci/svd2rust-regress/src/tests.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ pub enum Architecture {
77
CortexM,
88
Msp430,
99
RiscV,
10-
XtensaLX6,
10+
XtensaLX,
1111
}
1212

1313
#[derive(Debug)]
@@ -4229,7 +4229,7 @@ pub const TESTS: &[&TestCase] = &[
42294229
run_when: Always,
42304230
},
42314231
&TestCase {
4232-
arch: XtensaLX6,
4232+
arch: XtensaLX,
42334233
mfgr: Espressif,
42344234
chip: "esp32",
42354235
svd_url: Some(

src/generate/device.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -198,7 +198,7 @@ pub fn render(
198198
Target::CortexM => Some(Ident::new("cortex_m", span)),
199199
Target::Msp430 => Some(Ident::new("msp430", span)),
200200
Target::RISCV => Some(Ident::new("riscv", span)),
201-
Target::XtensaLX6 => Some(Ident::new("xtensa_lx6", span)),
201+
Target::XtensaLX => Some(Ident::new("xtensa_lx", span)),
202202
Target::None => None,
203203
}
204204
.map(|krate| {

src/generate/interrupt.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -126,7 +126,7 @@ pub fn render(
126126
});
127127
}
128128
Target::RISCV => {}
129-
Target::XtensaLX6 => {
129+
Target::XtensaLX => {
130130
for name in &names {
131131
writeln!(device_x, "PROVIDE({} = DefaultHandler);", name)?;
132132
}
@@ -216,7 +216,7 @@ pub fn render(
216216
_ => "C",
217217
};
218218

219-
if target != Target::CortexM && target != Target::Msp430 && target != Target::XtensaLX6 {
219+
if target != Target::CortexM && target != Target::Msp430 && target != Target::XtensaLX {
220220
mod_items.extend(quote! {
221221
#[cfg(feature = "rt")]
222222
#[macro_export]

src/lib.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,7 @@
2020
//!
2121
//! `svd2rust` supports Cortex-M, MSP430, RISCV and Xtensa LX6 microcontrollers. The generated crate can
2222
//! be tailored for either architecture using the `--target` flag. The flag accepts "cortex-m",
23-
//! "msp430", "riscv", "xtensalx6" and "none" as values. "none" can be used to generate a crate that's
23+
//! "msp430", "riscv", "xtensa-lx" and "none" as values. "none" can be used to generate a crate that's
2424
//! architecture agnostic and that should work for architectures that `svd2rust` doesn't currently
2525
//! know about like the Cortex-A architecture.
2626
//!

src/main.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -100,7 +100,7 @@ fn run() -> Result<()> {
100100
file.write_all(data.as_ref())
101101
.expect("Could not write code to lib.rs");
102102

103-
if target == Target::CortexM || target == Target::Msp430 || target == Target::XtensaLX6 {
103+
if target == Target::CortexM || target == Target::Msp430 || target == Target::XtensaLX {
104104
writeln!(File::create("device.x")?, "{}", device_x)?;
105105
writeln!(File::create("build.rs")?, "{}", build_rs())?;
106106
}

src/util.rs

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ pub enum Target {
1818
CortexM,
1919
Msp430,
2020
RISCV,
21-
XtensaLX6,
21+
XtensaLX,
2222
None,
2323
}
2424

@@ -28,7 +28,7 @@ impl Target {
2828
"cortex-m" => Target::CortexM,
2929
"msp430" => Target::Msp430,
3030
"riscv" => Target::RISCV,
31-
"xtensalx6" => Target::XtensaLX6,
31+
"xtensa-lx" => Target::XtensaLX,
3232
"none" => Target::None,
3333
_ => bail!("unknown target {}", s),
3434
})

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