cortex-m-pac crate: standard traits and result handling for Cortex-M targets
#560
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| /// Represents error variants for the library. | ||
| #[derive(Clone, Copy, Debug, Eq, PartialEq)] | ||
| pub enum Error { |
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since core::error::Error is now stable it might make sense to impl it here? since you already have impl core::fmt::Display this should be straight-forward?
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Implementing |
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CI failed because the ubuntu-latest label migrated to ubuntu 24.04 (https://github.blog/changelog/2024-09-25-actions-new-images-and-ubuntu-latest-changes/), and it looks like there the qemu package is no longer available. A quick fix would be to change the runner image to Alternatively, CI could use |
That was easier than I had expected: #562 |
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Rebased and added |
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| ## Minimum Supported Rust Version (MSRV) | ||
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| This crate is guaranteed to compile on stable Rust 1.60 and up. It *might* |
| /// * `MAX_EXCEPTION_NUMBER` must coincide with the highest allowed exception number. | ||
| pub unsafe trait ExceptionNumber: Copy { | ||
| /// Highest number assigned to an exception. | ||
| const MAX_EXCEPTION_NUMBER: usize; |
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It seems strange to define MAX_EXCEPTION_NUMBER on each instance of ExceptionNumber.
Sorry, I misunderstood the purpose. There should only be one enum implementing this trait, right?
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| ## License | ||
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| Copyright 2024 [Cortex-M team][team] |
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CC @adamgreig Since this is replacing a previous PR from you. |
This PR ports some of the ongoing work in the RISC-V ecosystem to Cortex-M targets. Namely, I adapted the
riscv-paccrate to the newcortex-m-paccrate.The main purpose of this crate is to isolate fundamental traits and data types from potential breaking changes in
cortex-m. Namely, it currently contains traits for enumerating exceptions, interrupts, priorities, and core IDs. It also provides a basic fallible function support for Cortex-M devices, with an error enum with some of the most typical issues developers may face.Related PRs in RISC-V: #222 and #223
Related PRs in Cortex-M: #488
Once this is merged, I plan to continue porting new functionalities from RISC-V to Cortex-M (e.g., new syntax for interrupt and exception macros)