diff --git a/Cargo.toml b/Cargo.toml
index 540b67c9..c54dabf1 100644
--- a/Cargo.toml
+++ b/Cargo.toml
@@ -21,6 +21,5 @@ bare-metal = { version = "0.2.0", features = ["const-fn"] }
 volatile-register = "0.2.0"
 
 [features]
-const-fn = []
 cm7-r0p1 = []
 inline-asm = []
diff --git a/src/peripheral/nvic.rs b/src/peripheral/nvic.rs
index 1ecfc6e5..6627e60c 100644
--- a/src/peripheral/nvic.rs
+++ b/src/peripheral/nvic.rs
@@ -38,7 +38,6 @@ pub struct RegisterBlock {
 
     _reserved5: [u32; 48],
 
-    #[cfg(not(armv6m))]
     /// Interrupt Priority
     ///
     /// On ARMv7-M, 124 word-sized registers are available. Each of those
@@ -50,9 +49,9 @@ pub struct RegisterBlock {
     /// On ARMv6-M, the registers must only be accessed along word boundaries,
     /// so convenient byte-sized representation wouldn't work on that
     /// architecture.
+    #[cfg(not(armv6m))]
     pub ipr: [RW<u8>; 496],
 
-    #[cfg(armv6m)]
     /// Interrupt Priority
     ///
     /// On ARMv7-M, 124 word-sized registers are available. Each of those
@@ -64,18 +63,18 @@ pub struct RegisterBlock {
     /// On ARMv6-M, the registers must only be accessed along word boundaries,
     /// so convenient byte-sized representation wouldn't work on that
     /// architecture.
+    #[cfg(armv6m)]
     pub ipr: [RW<u32>; 8],
 
     #[cfg(not(armv6m))]
     _reserved6: [u32; 580],
 
-    #[cfg(not(armv6m))]
     /// Software Trigger Interrupt
+    #[cfg(not(armv6m))]
     pub stir: WO<u32>,
 }
 
 impl NVIC {
-    #[cfg(not(armv6m))]
     /// Request an IRQ in software
     ///
     /// Writing a value to the INTID field is the same as manually pending an interrupt by setting
@@ -83,6 +82,7 @@ impl NVIC {
     /// `set_pending`.
     ///
     /// This method is not available on ARMv6-M chips.
+    #[cfg(not(armv6m))]
     #[inline]
     pub fn request<I>(&mut self, interrupt: I)
     where
@@ -95,16 +95,6 @@ impl NVIC {
         }
     }
 
-    /// Clears `interrupt`'s pending state
-    #[deprecated(since = "0.5.8", note = "Use `NVIC::unpend`")]
-    #[inline]
-    pub fn clear_pending<I>(&mut self, interrupt: I)
-    where
-        I: Nr,
-    {
-        Self::unpend(interrupt)
-    }
-
     /// Disables `interrupt`
     #[inline]
     pub fn mask<I>(interrupt: I)
@@ -129,27 +119,6 @@ impl NVIC {
         (*Self::ptr()).iser[usize::from(nr / 32)].write(1 << (nr % 32))
     }
 
-    /// Disables `interrupt`
-    #[deprecated(since = "0.6.1", note = "Use `NVIC::mask`")]
-    #[inline]
-    pub fn disable<I>(&mut self, interrupt: I)
-    where
-        I: Nr,
-    {
-        Self::mask(interrupt)
-    }
-
-    /// **WARNING** This method is a soundness hole in the API; it should actually be an `unsafe`
-    /// function. Use `NVIC::unmask` which has the right unsafety.
-    #[deprecated(since = "0.6.1", note = "Use `NVIC::unmask`")]
-    #[inline]
-    pub fn enable<I>(&mut self, interrupt: I)
-    where
-        I: Nr,
-    {
-        unsafe { Self::unmask(interrupt) }
-    }
-
     /// Returns the NVIC priority of `interrupt`
     ///
     /// *NOTE* NVIC encodes priority in the highest bits of a byte so values like `1` and `2` map
@@ -228,16 +197,6 @@ impl NVIC {
         unsafe { (*Self::ptr()).ispr[usize::from(nr / 32)].write(1 << (nr % 32)) }
     }
 
-    /// Forces `interrupt` into pending state
-    #[deprecated(since = "0.5.8", note = "Use `NVIC::pend`")]
-    #[inline]
-    pub fn set_pending<I>(&mut self, interrupt: I)
-    where
-        I: Nr,
-    {
-        Self::pend(interrupt)
-    }
-
     /// Sets the "priority" of `interrupt` to `prio`
     ///
     /// *NOTE* See [`get_priority`](struct.NVIC.html#method.get_priority) method for an explanation
diff --git a/src/peripheral/scb.rs b/src/peripheral/scb.rs
index 9d58b038..b2f45c57 100644
--- a/src/peripheral/scb.rs
+++ b/src/peripheral/scb.rs
@@ -633,27 +633,6 @@ const SCB_AIRCR_PRIGROUP_MASK: u32 = 0x5 << 8;
 const SCB_AIRCR_SYSRESETREQ: u32 = 1 << 2;
 
 impl SCB {
-    /// Initiate a system reset request to reset the MCU
-    #[deprecated(since = "0.6.1", note = "Use `SCB::sys_reset`")]
-    #[inline]
-    pub fn system_reset(&mut self) -> ! {
-        crate::asm::dsb();
-        unsafe {
-            self.aircr.modify(
-                |r| {
-                    SCB_AIRCR_VECTKEY | // otherwise the write is ignored
-            r & SCB_AIRCR_PRIGROUP_MASK | // keep priority group unchanged
-            SCB_AIRCR_SYSRESETREQ
-                }, // set the bit
-            )
-        };
-        crate::asm::dsb();
-        loop {
-            // wait for the reset
-            crate::asm::nop(); // avoid rust-lang/rust#28728
-        }
-    }
-
     /// Initiate a system reset request to reset the MCU
     #[inline]
     pub fn sys_reset() -> ! {
diff --git a/src/register/mod.rs b/src/register/mod.rs
index e7879c5c..d69c1a51 100644
--- a/src/register/mod.rs
+++ b/src/register/mod.rs
@@ -29,35 +29,14 @@
 #[cfg(all(not(armv6m), not(armv8m_base)))]
 pub mod basepri;
 
-#[cfg(armv8m_base)]
-#[deprecated(
-    since = "0.6.2",
-    note = "basepri is unavailable on thumbv8.base, and will be removed in the next release"
-)]
-pub mod basepri;
-
 #[cfg(all(not(armv6m), not(armv8m_base)))]
 pub mod basepri_max;
 
-#[cfg(armv8m_base)]
-#[deprecated(
-    since = "0.6.2",
-    note = "basepri is unavailable on thumbv8m.base, and will be removed in the next release"
-)]
-pub mod basepri_max;
-
 pub mod control;
 
 #[cfg(all(not(armv6m), not(armv8m_base)))]
 pub mod faultmask;
 
-#[cfg(armv8m_base)]
-#[deprecated(
-    since = "0.6.2",
-    note = "faultmask is unavailable on thumbv8m.base, and will be removed in the next release"
-)]
-pub mod faultmask;
-
 pub mod msp;
 
 pub mod primask;