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1 parent a9a6f55 commit f2a1d92Copy full SHA for f2a1d92
src/peripheral/dcb.rs
@@ -3,8 +3,6 @@
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use volatile_register::{RW, WO};
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use crate::peripheral::DCB;
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-#[allow(unused_imports)]
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-use crate::peripheral::{DWT, ITM};
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use core::ptr;
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const DCB_DEMCR_TRCENA: u32 = 1 << 24;
@@ -24,7 +22,8 @@ pub struct RegisterBlock {
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}
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impl DCB {
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- /// Global enable for all [`DWT`] and [`ITM`] features.
+ /// Global enable for all [`DWT`](crate::peripheral::DWT) and
+ /// [`ITM`](crate::peripheral::ITM) features.
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///
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/// Note: vendor-specific registers may have to be set to completely
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/// enable tracing. For example, on the STM32F401RE, `TRACE_MODE`
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