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[[atomics]]
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== "A" Extension for Atomic Instructions, Version 2.1
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- The standard atomic-instruction extension, named "A", contains
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+ The atomic-instruction extension, named "A", contains
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instructions that atomically read-modify-write memory to support
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synchronization between multiple RISC-V harts running in the same memory
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space. The two forms of atomic instruction provided are
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memory consistency model and so the RISC-V atomic support is built
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around this model.
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====
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+
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+ The A extension comprises instructions provided by the Zaamo and Zalrsc
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+ extensions.
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+
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=== Specifying Ordering of Atomic Instructions
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The base RISC-V ISA has a relaxed memory model, with the FENCE
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same address domain.
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[[sec:lrsc]]
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- === Load-Reserved/Store-Conditional Instructions
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+ === "Zalrsc" Extension for Load-Reserved/Store-Conditional Instructions
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include::images/wavedrom/load-reserve-st-conditional.adoc[]
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@@ -114,7 +118,7 @@ for the SLT/SLTU instructions. More specific failure codes might be
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defined in future versions or extensions to the ISA.
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====
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- For LR and SC, the A extension requires that the address held in _rs1_
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+ For LR and SC, the Zalrsc extension requires that the address held in _rs1_
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be naturally aligned to the size of the operand (i.e., eight-byte
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aligned for _doublewords_ and four-byte aligned for _words_). If the
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address is not naturally aligned, an address-misaligned exception or an
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[[sec:lrscseq]]
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=== Eventual Success of Store-Conditional Instructions
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- The standard A extension defines _constrained LR/SC loops_, which have
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+ The Zalrsc extension defines _constrained LR/SC loops_, which have
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the following properties:
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* The loop comprises only an LR/SC sequence and code to retry the
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====
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[[sec:amo]]
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- === Atomic Memory Operations
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+ === "Zaamo" Extension for Atomic Memory Operations
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include::images/wavedrom/atomic-mem.adoc[]
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@@ -363,7 +367,7 @@ can either operate on _doublewords_ (RV64 only) or _words_ in memory. For
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RV64, 32-bit AMOs always sign-extend the value placed in _rd_, and
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ignore the upper 32 bits of the original value of _rs2_.
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- For AMOs, the A extension requires that the address held in _rs1_ be
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+ For AMOs, the Zaamo extension requires that the address held in _rs1_ be
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naturally aligned to the size of the operand (i.e., eight-byte aligned
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for _doublewords_ and four-byte aligned for _words_). If the address
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is not naturally aligned, an address-misaligned exception or an
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memory. Another use of AMOs is to provide atomic updates to
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memory-mapped device registers (e.g., setting, clearing, or toggling
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bits) in the I/O space.
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+ The Zaamo extension enables microcontroller class implementations to utilize
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+ atomic primitives from the AMO subset of the A extension. Typically such
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+ implementations do not have caches and thus may not be able to naturally support
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+ the LR/SC instructions provided by the Zalrsc extension.
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====
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To help implement multiprocessor synchronization, the AMOs optionally
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