Merge pull request #1339 from riscv/chapter-titles-cleanup

Chapter titles cleanup

Author: wmat

src/a-st-ext.adoc

@@ -1,5 +1,5 @@
 [[atomics]]
-== "A" Standard Extension for Atomic Instructions, Version 2.1
+== "A" Extension for Atomic Instructions, Version 2.1
 
 The standard atomic-instruction extension, named "A", contains
 instructions that atomically read-modify-write memory to support

src/b-st-ext.adoc

@@ -1,5 +1,5 @@
 [[bits]]
-== "B" Standard Extension for Bit Manipulation, Version 1.0.0
+== "B" Extension for Bit Manipulation, Version 1.0.0
 
 The B standard extension comprises instructions provided by the Zba, Zbb, and
 Zbs extensions.

src/c-st-ext.adoc

@@ -1,5 +1,5 @@
 [[compressed]]
-== "C" Standard Extension for Compressed Instructions, Version 2.0
+== "C" Extension for Compressed Instructions, Version 2.0
 
 This chapter describes the RISC-V standard compressed instruction-set
 extension, named "C", which reduces static and dynamic code size by

src/cmo.adoc

@@ -1,5 +1,5 @@
 [[cmo]]
-== Base Cache Management Operation ISA Extensions
+== "CMO" Extensions for Base Cache Management Operation ISA, Version 1.0.0
 
 === Pseudocode for instruction semantics
 

src/counters.adoc

@@ -1,13 +1,13 @@
 [[counters]]
-== "Zicntr" and "Zihpm" Counters, Version 2.0
+== "Zicntr" and "Zihpm" Extensions for Counters, Version 2.0
 
 RISC-V ISAs provide a set of up to thirty-two 64-bit performance
 counters and timers that are accessible via unprivileged XLEN-bit
 read-only CSR registers `0xC00`–`0xC1F` (when XLEN=32, the upper 32 bits
 are accessed via CSR registers `0xC80`–`0xC9F`). These counters are
 divided between the "Zicntr" and "Zihpm" extensions.
 
-=== "Zicntr" Standard Extension for Base Counters and Timers
+=== "Zicntr" Extension for Base Counters and Timers
 
 The Zicntr standard extension comprises the first three of these
 counters (CYCLE, TIME, and INSTRET), which have dedicated functions
@@ -173,7 +173,7 @@ reading its upper and lower halves.
         bne          x3, x4, again
 
 
-=== "Zihpm" Standard Extension for Hardware Performance Counters
+=== "Zihpm" Extension for Hardware Performance Counters
 
 The Zihpm extension comprises up to 29 additional unprivileged 64-bit
 hardware performance counters, `hpmcounter3-hpmcounter31`. When

src/d-st-ext.adoc

@@ -1,4 +1,4 @@
-== "D" Standard Extension for Double-Precision Floating-Point, Version 2.2
+== "D" Extension for Double-Precision Floating-Point, Version 2.2
 
 This chapter describes the standard double-precision floating-point
 instruction-set extension, which is named "D" and adds

src/f-st-ext.adoc

@@ -1,7 +1,7 @@
 :stem: latexmath
 
 [[single-float]]
-== "F" Standard Extension for Single-Precision Floating-Point, Version 2.2
+== "F" Extension for Single-Precision Floating-Point, Version 2.2
 
 This chapter describes the standard instruction-set extension for
 single-precision floating-point, which is named "F" and adds

src/j-st-ext.adoc

@@ -1,5 +1,5 @@
 [[j-extendj]]
-==  "J" Standard Extension for Dynamically Translated Languages, Version 0.0
+==  "J"  Extension for Dynamically Translated Languages, Version 0.0
 
 This chapter is a placeholder for a future standard extension to support
 dynamically translated languages.

src/m-st-ext.adoc

@@ -1,5 +1,5 @@
 [[mstandard]]
-== "M" Standard Extension for Integer Multiplication and Division, Version 2.0
+== "M" Extension for Integer Multiplication and Division, Version 2.0
 
 This chapter describes the standard integer multiplication and division
 instruction extension, which is named "M" and contains instructions

src/p-st-ext.adoc

@@ -1,5 +1,5 @@
 [[packedsimd]]
-== "P" Standard Extension for Packed-SIMD Instructions, Version 0.2
+== "P" Extension for Packed-SIMD Instructions, Version 0.2
 [NOTE]
 ====
 Discussions at the 5th RISC-V workshop indicated a desire to drop this

src/q-st-ext.adoc

@@ -1,4 +1,4 @@
-== "Q" Standard Extension for Quad-Precision Floating-Point, Version 2.2
+== "Q" Extension for Quad-Precision Floating-Point, Version 2.2
 
 This chapter describes the Q standard extension for 128-bit
 quad-precision binary floating-point instructions compliant with the

src/rnmi.adoc

@@ -1,5 +1,5 @@
 [[rnmi]]
-== "Smrnmi" Standard Extension for Resumable Non-Maskable Interrupts, Version 0.5
+== "Smrnmi" Extension for Resumable Non-Maskable Interrupts, Version 0.5
 
 [WARNING]
 ====

src/scalar-crypto.adoc

@@ -1,4 +1,4 @@
-== Cryptography Extensions Volume I: Scalar & Entropy Source Instructions, Version 1.0.1
+== Cryptography Extensions: Scalar & Entropy Source Instructions, Version 1.0.1
 
 === Changelog
 

src/smepmp.adoc

@@ -1,5 +1,5 @@
 [[smepmp]]
-== PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp)
+== "Smepmp" Extension for PMP Enhancements for memory access and execution prevention in Machine mode, Version 1.0.0
 === Introduction
 
 Being able to access the memory of a process running at a high privileged execution mode, such as the Supervisor or Machine mode, from a lower privileged mode such as the User mode, introduces an obvious attack vector since it allows for an attacker to perform privilege escalation, and tamper with the code and/or data of that process. A less obvious attack vector exists when the reverse happens, in which case an attacker instead of tampering with code and/or data that belong to a high-privileged process, can tamper with the memory of an unprivileged / less-privileged process and trick the high-privileged process to use or execute it.

src/sscofpmf.adoc

@@ -1,5 +1,5 @@
 [[Sscofpmf]]
-== "Sscofpmf" Count Overflow and Mode-Based Filtering Extension, Version 1.0.0
+== "Sscofpmf" Extension for Count Overflow and Mode-Based Filtering, Version 1.0.0
 
 The current Privileged specification defines mhpmevent CSRs to select and
 control event counting by the associated hpmcounter CSRs, but provides no

src/sstc.adoc

@@ -1,5 +1,5 @@
 [[Sstc]]
-== Sstc Standard Extension for Supervisor-mode Timer Interrupts, Version 1.0.0
+== "Sstc" Extension for Supervisor-mode Timer Interrupts, Version 1.0.0
 
 The current Privileged arch specification only defines a hardware mechanism for
 generating machine-mode timer interrupts (based on the mtime and mtimecmp

src/supervisor.adoc

@@ -1670,7 +1670,7 @@ in <<sv32algorithm>>, except LEVELS equals 5 and
 PTESIZE equals 8.
 
 [[svnapot]]
-== "Svnapot" Standard Extension for NAPOT Translation Contiguity, Version 1.0
+== "Svnapot" Extension for NAPOT Translation Contiguity, Version 1.0
 
 In Sv39, Sv48, and Sv57, when a PTE has N=1, the PTE represents a
 translation that is part of a range of contiguous virtual-to-physical
@@ -1836,7 +1836,7 @@ first step.
 ====
 
 [[svpbmt]]
-== "Svpbmt" Standard Extension for Page-Based Memory Types, Version 1.0
+== "Svpbmt" Extension for Page-Based Memory Types, Version 1.0
 
 In Sv39, Sv48, and Sv57, bits 62-61 of a leaf page table entry indicate
 the use of page-based memory types that override the PMA(s) for the
@@ -1962,7 +1962,7 @@ attributes used by accesses to the page in question. Otherwise, the
 intermediate attributes are used as the final set of attributes.
 
 [[svinval]]
-== "Svinval" Standard Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0
+== "Svinval" Extension for Fine-Grained Address-Translation Cache Invalidation, Version 1.0
 
 The Svinval extension splits SFENCE.VMA, HFENCE.VVMA, and HFENCE.GVMA
 instructions into finer-grained invalidation and ordering operations
@@ -2054,7 +2054,7 @@ instructions as no-ops.
 ====
 
 [[sec:svadu]]
-== "Svadu" Standard Extension for Hardware Updating of A/D Bits, Version 1.0
+== "Svadu" Extension for Hardware Updating of A/D Bits, Version 1.0
 
 The Svadu extension adds support and CSR controls for hardware updating of PTE A/D bits.
 
@@ -2069,7 +2069,7 @@ exceptions when A/D bits need be set, instead takes effect.
 The Svade extension is also defined in <<translation>>.
 
 [[sec:svvptc]]
-== "Svvptc" Standard Extension for Eliding Memory-Management Fences on Making PTEs Valid, Version 1.0
+== "Svvptc" Extension for Eliding Memory-Management Fences on Making PTEs Valid, Version 1.0
 
 When the Svvptc extension is implemented, explicit stores that update the Valid
 bit of leaf and/or non-leaf PTEs from 0 to 1 and are visible to a hart will
@@ -2096,7 +2096,7 @@ fence instructions outweighs the occasional cost of a gratuitous page-fault.
 
 ////
 [[sec:ssqosid]]
-== "Ssqosid" Standard Extension for Quality-of-Service (QoS) Identifiers, Version 1.0
+== "Ssqosid" Extension for Quality-of-Service (QoS) Identifiers, Version 1.0
 
 Quality of Service (QoS) is defined as the minimal end-to-end performance
 guaranteed in advance by a service level agreement (SLA) to a workload.

src/vector-crypto.adoc

@@ -1,4 +1,4 @@
-== Cryptography Extensions Volume II: Vector Instructions, Version 1.0.0
+== Cryptography Extensions: Vector Instructions, Version 1.0.0
 
 This document describes the Vector Cryptography extensions to the 
 RISC-V Instruction Set Architecture.

src/zacas.adoc

@@ -1,4 +1,4 @@
-== Atomic Compare-and-Swap (CAS) instructions (Zacas), Version 1.0.0
+== "Zacas" Extension for Atomic Compare-and-Swap (CAS) Instructions, Version 1.0.0
 
 === Introduction
 

src/zawrs.adoc

@@ -1,4 +1,4 @@
-== "Zawrs" Standard extension for Wait-on-Reservation-Set instructions, Version 1.01
+== "Zawrs" Extension for Wait-on-Reservation-Set instructions, Version 1.01
 
 The Zawrs extension defines a pair of instructions to be used in polling loops 
 that allows a core to enter a low-power state and wait on a store to a memory 

src/zc.adoc

@@ -1,5 +1,5 @@
 [#Zc]
-== "Zc*" Standard Extension for Code Size Reduction
+== "Zc*" Extension for Code Size Reduction, Version 1.0.0
 
 === Zc* Overview
 

src/zfa.adoc

@@ -1,5 +1,5 @@
 [[zfa]]
-== "Zfa" Standard Extension for Additional Floating-Point Instructions, Version 1.0
+== "Zfa" Extension for Additional Floating-Point Instructions, Version 1.0
 
 This chapter describes the Zfa standard extension, which adds
 instructions for immediate loads, IEEE 754-2019 minimum and maximum

src/zfh.adoc

@@ -1,4 +1,4 @@
-== "Zfh" and "Zfhmin" Standard Extensions for Half-Precision Floating-Point, Version 1.0
+== "Zfh" and "Zfhmin" Extensions for Half-Precision Floating-Point, Version 1.0
 
 This chapter describes the Zfh standard extension for 16-bit
 half-precision binary floating-point instructions compliant with the

src/zfinx.adoc

@@ -1,5 +1,5 @@
 [[sec:zfinx]]
-== "Zfinx", "Zdinx", "Zhinx", "Zhinxmin": Standard Extensions for Floating-Point in Integer Registers, Version 1.0
+== "Zfinx", "Zdinx", "Zhinx", "Zhinxmin" Extensions for Floating-Point in Integer Registers, Version 1.0
 
 This chapter defines the "Zfinx" extension (pronounced "z-f-in-x")
 that provides instructions similar to those in the standard

src/zicond.adoc

@@ -1,5 +1,5 @@
 [[Zicond]]
-== "Zicond" Integer Conditional operations extension
+== "Zicond" Extension for Integer Conditional Operations, Version 1.0.0
 
 [[intro]]
 === Introduction

src/zicsr.adoc

@@ -1,5 +1,5 @@
 [[csrinsts]]
-== "Zicsr", Control and Status Register (CSR) Instructions, Version 2.0
+== "Zicsr", Extension for Control and Status Register (CSR) Instructions, Version 2.0
 
 RISC-V defines a separate address space of 4096 Control and Status
 registers associated with each hart. This chapter defines the full set

src/zifencei.adoc

@@ -1,5 +1,5 @@
 [[zifencei]]
-== "Zifencei" Instruction-Fetch Fence, Version 2.0
+== "Zifencei" Extension for Instruction-Fetch Fence, Version 2.0
 This chapter defines the "Zifencei" extension, which includes the
 FENCE.I instruction that provides explicit synchronization between
 writes to instruction memory and instruction fetches on the same hart.

src/zihintntl.adoc

@@ -1,5 +1,5 @@
 [[chap:zihintntl]]
-== "Zihintntl" Non-Temporal Locality Hints, Version 1.0
+== "Zihintntl" Extension for Non-Temporal Locality Hints, Version 1.0
 
 The NTL instructions are HINTs that indicate that the explicit memory
 accesses of the immediately subsequent instruction (henceforth "target

src/zihintpause.adoc

@@ -1,5 +1,5 @@
 [[zihintpause]]
-== "Zihintpause" Pause Hint, Version 2.0
+== "Zihintpause" Extension for Pause Hint, Version 2.0
 The PAUSE instruction is a HINT that indicates the current hart's rate
 of instruction retirement should be temporarily reduced or paused. The
 duration of its effect must be bounded and may be zero.

src/zimop.adoc

@@ -1,5 +1,5 @@
 [[zimop]]
-== "Zimop" May-Be-Operations Extension, Version 1.0
+== "Zimop" Extension for May-Be-Operations, Version 1.0
 
 This chapter defines the "Zimop" extension, which introduces the concept of
 instructions that _may be operations_ (MOPs).  MOPs are initially defined to

src/ztso-st-ext.adoc

@@ -1,5 +1,5 @@
 [[ztso]]
-== "Ztso" Standard Extension for Total Store Ordering, Version 1.0 
+== "Ztso" Extension for Total Store Ordering, Version 1.0 
 
 This chapter defines the "Ztso" extension for the RISC-V Total Store
 Ordering (RVTSO) memory consistency model. RVTSO is defined as a delta