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xtensa.c
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// SPDX-License-Identifier: GPL-2.0-or-later
/***************************************************************************
* Generic Xtensa target API for OpenOCD *
* Copyright (C) 2020-2022 Cadence Design Systems, Inc. *
* Copyright (C) 2016-2019 Espressif Systems Ltd. *
* Derived from esp108.c *
* Author: Angus Gratton [email protected] *
***************************************************************************/
#ifdef HAVE_CONFIG_H
#include "config.h"
#endif
#include <stdlib.h>
#include <helper/time_support.h>
#include <helper/align.h>
#include <target/register.h>
#include "xtensa_chip.h"
#include "xtensa.h"
/* Swap 4-bit Xtensa opcodes and fields */
#define XT_NIBSWAP8(V) \
((((V) & 0x0F) << 4) \
| (((V) & 0xF0) >> 4))
#define XT_NIBSWAP16(V) \
((((V) & 0x000F) << 12) \
| (((V) & 0x00F0) << 4) \
| (((V) & 0x0F00) >> 4) \
| (((V) & 0xF000) >> 12))
#define XT_NIBSWAP24(V) \
((((V) & 0x00000F) << 20) \
| (((V) & 0x0000F0) << 12) \
| (((V) & 0x000F00) << 4) \
| (((V) & 0x00F000) >> 4) \
| (((V) & 0x0F0000) >> 12) \
| (((V) & 0xF00000) >> 20))
/* _XT_INS_FORMAT_*()
* Instruction formatting converted from little-endian inputs
* and shifted to the MSB-side of DIR for BE systems.
*/
#define _XT_INS_FORMAT_RSR(X, OPCODE, SR, T) \
(XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \
| (((T) & 0x0F) << 16) \
| (((SR) & 0xFF) << 8)) << 8 \
: (OPCODE) \
| (((SR) & 0xFF) << 8) \
| (((T) & 0x0F) << 4))
#define _XT_INS_FORMAT_RRR(X, OPCODE, ST, R) \
(XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \
| ((XT_NIBSWAP8((ST) & 0xFF)) << 12) \
| (((R) & 0x0F) << 8)) << 8 \
: (OPCODE) \
| (((ST) & 0xFF) << 4) \
| (((R) & 0x0F) << 12))
#define _XT_INS_FORMAT_RRRN(X, OPCODE, S, T, IMM4) \
(XT_ISBE(X) ? (XT_NIBSWAP16(OPCODE) \
| (((T) & 0x0F) << 8) \
| (((S) & 0x0F) << 4) \
| ((IMM4) & 0x0F)) << 16 \
: (OPCODE) \
| (((T) & 0x0F) << 4) \
| (((S) & 0x0F) << 8) \
| (((IMM4) & 0x0F) << 12))
#define _XT_INS_FORMAT_RRI8(X, OPCODE, R, S, T, IMM8) \
(XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \
| (((T) & 0x0F) << 16) \
| (((S) & 0x0F) << 12) \
| (((R) & 0x0F) << 8) \
| ((IMM8) & 0xFF)) << 8 \
: (OPCODE) \
| (((IMM8) & 0xFF) << 16) \
| (((R) & 0x0F) << 12) \
| (((S) & 0x0F) << 8) \
| (((T) & 0x0F) << 4))
#define _XT_INS_FORMAT_RRI4(X, OPCODE, IMM4, R, S, T) \
(XT_ISBE(X) ? (XT_NIBSWAP24(OPCODE) \
| (((T) & 0x0F) << 16) \
| (((S) & 0x0F) << 12) \
| (((R) & 0x0F) << 8)) << 8 \
| ((IMM4) & 0x0F) \
: (OPCODE) \
| (((IMM4) & 0x0F) << 20) \
| (((R) & 0x0F) << 12) \
| (((S) & 0x0F) << 8) \
| (((T) & 0x0F) << 4))
/* Xtensa processor instruction opcodes
*/
/* "Return From Debug Operation" to Normal */
#define XT_INS_RFDO(X) (XT_ISBE(X) ? 0x000e1f << 8 : 0xf1e000)
/* "Return From Debug and Dispatch" - allow sw debugging stuff to take over */
#define XT_INS_RFDD(X) (XT_ISBE(X) ? 0x010e1f << 8 : 0xf1e010)
/* Load to DDR register, increase addr register */
#define XT_INS_LDDR32P(X, S) (XT_ISBE(X) ? (0x0E0700 | ((S) << 12)) << 8 : (0x0070E0 | ((S) << 8)))
/* Store from DDR register, increase addr register */
#define XT_INS_SDDR32P(X, S) (XT_ISBE(X) ? (0x0F0700 | ((S) << 12)) << 8 : (0x0070F0 | ((S) << 8)))
/* Load 32-bit Indirect from A(S)+4*IMM8 to A(T) */
#define XT_INS_L32I(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x002002, 0, S, T, IMM8)
/* Load 16-bit Unsigned from A(S)+2*IMM8 to A(T) */
#define XT_INS_L16UI(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x001002, 0, S, T, IMM8)
/* Load 8-bit Unsigned from A(S)+IMM8 to A(T) */
#define XT_INS_L8UI(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x000002, 0, S, T, IMM8)
/* Store 32-bit Indirect to A(S)+4*IMM8 from A(T) */
#define XT_INS_S32I(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x006002, 0, S, T, IMM8)
/* Store 16-bit to A(S)+2*IMM8 from A(T) */
#define XT_INS_S16I(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x005002, 0, S, T, IMM8)
/* Store 8-bit to A(S)+IMM8 from A(T) */
#define XT_INS_S8I(X, S, T, IMM8) _XT_INS_FORMAT_RRI8(X, 0x004002, 0, S, T, IMM8)
/* Cache Instructions */
#define XT_INS_IHI(X, S, IMM8) _XT_INS_FORMAT_RRI8(X, 0x0070E2, 0, S, 0, IMM8)
#define XT_INS_DHWBI(X, S, IMM8) _XT_INS_FORMAT_RRI8(X, 0x007052, 0, S, 0, IMM8)
#define XT_INS_DHWB(X, S, IMM8) _XT_INS_FORMAT_RRI8(X, 0x007042, 0, S, 0, IMM8)
#define XT_INS_ISYNC(X) (XT_ISBE(X) ? 0x000200 << 8 : 0x002000)
/* Control Instructions */
#define XT_INS_JX(X, S) (XT_ISBE(X) ? (0x050000 | ((S) << 12)) : (0x0000a0 | ((S) << 8)))
#define XT_INS_CALL0(X, IMM18) (XT_ISBE(X) ? (0x500000 | ((IMM18) & 0x3ffff)) : (0x000005 | (((IMM18) & 0x3ffff) << 6)))
/* Read Special Register */
#define XT_INS_RSR(X, SR, T) _XT_INS_FORMAT_RSR(X, 0x030000, SR, T)
/* Write Special Register */
#define XT_INS_WSR(X, SR, T) _XT_INS_FORMAT_RSR(X, 0x130000, SR, T)
/* Swap Special Register */
#define XT_INS_XSR(X, SR, T) _XT_INS_FORMAT_RSR(X, 0x610000, SR, T)
/* Rotate Window by (-8..7) */
#define XT_INS_ROTW(X, N) (XT_ISBE(X) ? ((0x000804) | (((N) & 15) << 16)) << 8 : ((0x408000) | (((N) & 15) << 4)))
/* Read User Register */
#define XT_INS_RUR(X, UR, T) _XT_INS_FORMAT_RRR(X, 0xE30000, UR, T)
/* Write User Register */
#define XT_INS_WUR(X, UR, T) _XT_INS_FORMAT_RSR(X, 0xF30000, UR, T)
/* Read Floating-Point Register */
#define XT_INS_RFR(X, FR, T) _XT_INS_FORMAT_RRR(X, 0xFA0000, ((FR << 4) | 0x4), T)
/* Write Floating-Point Register */
#define XT_INS_WFR(X, FR, T) _XT_INS_FORMAT_RRR(X, 0xFA0000, ((T << 4) | 0x5), FR)
#define XT_INS_L32E(X, R, S, T) _XT_INS_FORMAT_RRI4(X, 0x090000, 0, R, S, T)
#define XT_INS_S32E(X, R, S, T) _XT_INS_FORMAT_RRI4(X, 0x490000, 0, R, S, T)
#define XT_INS_L32E_S32E_MASK(X) (XT_ISBE(X) ? 0xF000FF << 8 : 0xFF000F)
#define XT_INS_RFWO(X) (XT_ISBE(X) ? 0x004300 << 8 : 0x003400)
#define XT_INS_RFWU(X) (XT_ISBE(X) ? 0x005300 << 8 : 0x003500)
#define XT_INS_RFWO_RFWU_MASK(X) (XT_ISBE(X) ? 0xFFFFFF << 8 : 0xFFFFFF)
#define XT_WATCHPOINTS_NUM_MAX 2
/* Special register number macro for DDR, PS, WB, A3, A4 registers.
* These get used a lot so making a shortcut is useful.
*/
#define XT_SR_DDR (xtensa_regs[XT_REG_IDX_DDR].reg_num)
#define XT_SR_PS (xtensa_regs[XT_REG_IDX_PS].reg_num)
#define XT_SR_WB (xtensa_regs[XT_REG_IDX_WINDOWBASE].reg_num)
#define XT_REG_A0 (xtensa_regs[XT_REG_IDX_AR0].reg_num)
#define XT_REG_A3 (xtensa_regs[XT_REG_IDX_AR3].reg_num)
#define XT_REG_A4 (xtensa_regs[XT_REG_IDX_AR4].reg_num)
#define XT_PS_REG_NUM (0xe6U)
#define XT_EPS_REG_NUM_BASE (0xc0U) /* (EPS2 - 2), for adding DBGLEVEL */
#define XT_EPC_REG_NUM_BASE (0xb0U) /* (EPC1 - 1), for adding DBGLEVEL */
#define XT_PC_REG_NUM_VIRTUAL (0xffU) /* Marker for computing PC (EPC[DBGLEVEL) */
#define XT_PC_DBREG_NUM_BASE (0x20U) /* External (i.e., GDB) access */
#define XT_NX_IBREAKC_BASE (0xc0U) /* (IBREAKC0..IBREAKC1) for NX */
#define XT_SW_BREAKPOINTS_MAX_NUM 32
#define XT_HW_IBREAK_MAX_NUM 2
#define XT_HW_DBREAK_MAX_NUM 2
struct xtensa_reg_desc xtensa_regs[XT_NUM_REGS] = {
XT_MK_REG_DESC("pc", XT_PC_REG_NUM_VIRTUAL, XT_REG_SPECIAL, 0),
XT_MK_REG_DESC("ar0", 0x00, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar1", 0x01, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar2", 0x02, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar3", 0x03, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar4", 0x04, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar5", 0x05, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar6", 0x06, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar7", 0x07, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar8", 0x08, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar9", 0x09, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar10", 0x0A, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar11", 0x0B, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar12", 0x0C, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar13", 0x0D, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar14", 0x0E, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar15", 0x0F, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar16", 0x10, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar17", 0x11, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar18", 0x12, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar19", 0x13, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar20", 0x14, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar21", 0x15, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar22", 0x16, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar23", 0x17, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar24", 0x18, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar25", 0x19, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar26", 0x1A, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar27", 0x1B, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar28", 0x1C, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar29", 0x1D, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar30", 0x1E, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar31", 0x1F, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar32", 0x20, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar33", 0x21, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar34", 0x22, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar35", 0x23, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar36", 0x24, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar37", 0x25, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar38", 0x26, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar39", 0x27, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar40", 0x28, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar41", 0x29, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar42", 0x2A, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar43", 0x2B, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar44", 0x2C, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar45", 0x2D, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar46", 0x2E, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar47", 0x2F, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar48", 0x30, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar49", 0x31, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar50", 0x32, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar51", 0x33, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar52", 0x34, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar53", 0x35, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar54", 0x36, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar55", 0x37, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar56", 0x38, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar57", 0x39, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar58", 0x3A, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar59", 0x3B, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar60", 0x3C, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar61", 0x3D, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar62", 0x3E, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("ar63", 0x3F, XT_REG_GENERAL, 0),
XT_MK_REG_DESC("windowbase", 0x48, XT_REG_SPECIAL, 0),
XT_MK_REG_DESC("windowstart", 0x49, XT_REG_SPECIAL, 0),
XT_MK_REG_DESC("ps", XT_PS_REG_NUM, XT_REG_SPECIAL, 0), /* PS (not mapped through EPS[]) */
XT_MK_REG_DESC("ibreakenable", 0x60, XT_REG_SPECIAL, 0),
XT_MK_REG_DESC("ddr", 0x68, XT_REG_DEBUG, XT_REGF_NOREAD),
XT_MK_REG_DESC("ibreaka0", 0x80, XT_REG_SPECIAL, 0),
XT_MK_REG_DESC("ibreaka1", 0x81, XT_REG_SPECIAL, 0),
XT_MK_REG_DESC("dbreaka0", 0x90, XT_REG_SPECIAL, 0),
XT_MK_REG_DESC("dbreaka1", 0x91, XT_REG_SPECIAL, 0),
XT_MK_REG_DESC("dbreakc0", 0xA0, XT_REG_SPECIAL, 0),
XT_MK_REG_DESC("dbreakc1", 0xA1, XT_REG_SPECIAL, 0),
XT_MK_REG_DESC("cpenable", 0xE0, XT_REG_SPECIAL, 0),
XT_MK_REG_DESC("exccause", 0xE8, XT_REG_SPECIAL, 0),
XT_MK_REG_DESC("debugcause", 0xE9, XT_REG_SPECIAL, 0),
XT_MK_REG_DESC("icount", 0xEC, XT_REG_SPECIAL, 0),
XT_MK_REG_DESC("icountlevel", 0xED, XT_REG_SPECIAL, 0),
/* WARNING: For these registers, regnum points to the
* index of the corresponding ARx registers, NOT to
* the processor register number! */
XT_MK_REG_DESC("a0", XT_REG_IDX_AR0, XT_REG_RELGEN, 0),
XT_MK_REG_DESC("a1", XT_REG_IDX_AR1, XT_REG_RELGEN, 0),
XT_MK_REG_DESC("a2", XT_REG_IDX_AR2, XT_REG_RELGEN, 0),
XT_MK_REG_DESC("a3", XT_REG_IDX_AR3, XT_REG_RELGEN, 0),
XT_MK_REG_DESC("a4", XT_REG_IDX_AR4, XT_REG_RELGEN, 0),
XT_MK_REG_DESC("a5", XT_REG_IDX_AR5, XT_REG_RELGEN, 0),
XT_MK_REG_DESC("a6", XT_REG_IDX_AR6, XT_REG_RELGEN, 0),
XT_MK_REG_DESC("a7", XT_REG_IDX_AR7, XT_REG_RELGEN, 0),
XT_MK_REG_DESC("a8", XT_REG_IDX_AR8, XT_REG_RELGEN, 0),
XT_MK_REG_DESC("a9", XT_REG_IDX_AR9, XT_REG_RELGEN, 0),
XT_MK_REG_DESC("a10", XT_REG_IDX_AR10, XT_REG_RELGEN, 0),
XT_MK_REG_DESC("a11", XT_REG_IDX_AR11, XT_REG_RELGEN, 0),
XT_MK_REG_DESC("a12", XT_REG_IDX_AR12, XT_REG_RELGEN, 0),
XT_MK_REG_DESC("a13", XT_REG_IDX_AR13, XT_REG_RELGEN, 0),
XT_MK_REG_DESC("a14", XT_REG_IDX_AR14, XT_REG_RELGEN, 0),
XT_MK_REG_DESC("a15", XT_REG_IDX_AR15, XT_REG_RELGEN, 0),
};
/**
* Types of memory used at xtensa target
*/
enum xtensa_mem_region_type {
XTENSA_MEM_REG_IROM = 0x0,
XTENSA_MEM_REG_IRAM,
XTENSA_MEM_REG_DROM,
XTENSA_MEM_REG_DRAM,
XTENSA_MEM_REG_SRAM,
XTENSA_MEM_REG_SROM,
XTENSA_MEM_REGS_NUM
};
/* Register definition as union for list allocation */
union xtensa_reg_val_u {
xtensa_reg_val_t val;
uint8_t buf[4];
};
static const struct xtensa_keyval_info_s xt_qerr[XT_QERR_NUM] = {
{ .chrval = "E00", .intval = ERROR_FAIL },
{ .chrval = "E01", .intval = ERROR_FAIL },
{ .chrval = "E02", .intval = ERROR_COMMAND_ARGUMENT_INVALID },
{ .chrval = "E03", .intval = ERROR_FAIL },
};
/* Set to true for extra debug logging */
static const bool xtensa_extra_debug_log;
/**
* Gets a config for the specific mem type
*/
static inline const struct xtensa_local_mem_config *xtensa_get_mem_config(
struct xtensa *xtensa,
enum xtensa_mem_region_type type)
{
switch (type) {
case XTENSA_MEM_REG_IROM:
return &xtensa->core_config->irom;
case XTENSA_MEM_REG_IRAM:
return &xtensa->core_config->iram;
case XTENSA_MEM_REG_DROM:
return &xtensa->core_config->drom;
case XTENSA_MEM_REG_DRAM:
return &xtensa->core_config->dram;
case XTENSA_MEM_REG_SRAM:
return &xtensa->core_config->sram;
case XTENSA_MEM_REG_SROM:
return &xtensa->core_config->srom;
default:
return NULL;
}
}
/**
* Extracts an exact xtensa_local_mem_region_config from xtensa_local_mem_config
* for a given address
* Returns NULL if nothing found
*/
static inline const struct xtensa_local_mem_region_config *xtensa_memory_region_find(
const struct xtensa_local_mem_config *mem,
target_addr_t address)
{
for (unsigned int i = 0; i < mem->count; i++) {
const struct xtensa_local_mem_region_config *region = &mem->regions[i];
if (address >= region->base && address < (region->base + region->size))
return region;
}
return NULL;
}
/**
* Returns a corresponding xtensa_local_mem_region_config from the xtensa target
* for a given address
* Returns NULL if nothing found
*/
static inline const struct xtensa_local_mem_region_config *xtensa_target_memory_region_find(
struct xtensa *xtensa,
target_addr_t address)
{
const struct xtensa_local_mem_region_config *result;
const struct xtensa_local_mem_config *mcgf;
for (unsigned int mtype = 0; mtype < XTENSA_MEM_REGS_NUM; mtype++) {
mcgf = xtensa_get_mem_config(xtensa, mtype);
result = xtensa_memory_region_find(mcgf, address);
if (result)
return result;
}
return NULL;
}
static inline bool xtensa_is_cacheable(const struct xtensa_cache_config *cache,
const struct xtensa_local_mem_config *mem,
target_addr_t address)
{
if (!cache->size)
return false;
return xtensa_memory_region_find(mem, address);
}
static inline bool xtensa_is_icacheable(struct xtensa *xtensa, target_addr_t address)
{
return xtensa_is_cacheable(&xtensa->core_config->icache, &xtensa->core_config->iram, address) ||
xtensa_is_cacheable(&xtensa->core_config->icache, &xtensa->core_config->irom, address) ||
xtensa_is_cacheable(&xtensa->core_config->icache, &xtensa->core_config->sram, address) ||
xtensa_is_cacheable(&xtensa->core_config->icache, &xtensa->core_config->srom, address);
}
static inline bool xtensa_is_dcacheable(struct xtensa *xtensa, target_addr_t address)
{
return xtensa_is_cacheable(&xtensa->core_config->dcache, &xtensa->core_config->dram, address) ||
xtensa_is_cacheable(&xtensa->core_config->dcache, &xtensa->core_config->drom, address) ||
xtensa_is_cacheable(&xtensa->core_config->dcache, &xtensa->core_config->sram, address) ||
xtensa_is_cacheable(&xtensa->core_config->dcache, &xtensa->core_config->srom, address);
}
static int xtensa_core_reg_get(struct reg *reg)
{
/* We don't need this because we read all registers on halt anyway. */
struct xtensa *xtensa = (struct xtensa *)reg->arch_info;
struct target *target = xtensa->target;
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
if (!reg->exist) {
if (strncmp(reg->name, "?0x", 3) == 0) {
unsigned int regnum = strtoul(reg->name + 1, NULL, 0);
LOG_WARNING("Read unknown register 0x%04x ignored", regnum);
return ERROR_OK;
}
return ERROR_COMMAND_ARGUMENT_INVALID;
}
return ERROR_OK;
}
static int xtensa_core_reg_set(struct reg *reg, uint8_t *buf)
{
struct xtensa *xtensa = (struct xtensa *)reg->arch_info;
struct target *target = xtensa->target;
assert(reg->size <= 64 && "up to 64-bit regs are supported only!");
if (target->state != TARGET_HALTED)
return ERROR_TARGET_NOT_HALTED;
if (!reg->exist) {
if (strncmp(reg->name, "?0x", 3) == 0) {
unsigned int regnum = strtoul(reg->name + 1, NULL, 0);
LOG_WARNING("Write unknown register 0x%04x ignored", regnum);
return ERROR_OK;
}
return ERROR_COMMAND_ARGUMENT_INVALID;
}
buf_cpy(buf, reg->value, reg->size);
if (xtensa->core_config->windowed) {
/* If the user updates a potential scratch register, track for conflicts */
for (enum xtensa_ar_scratch_set_e s = 0; s < XT_AR_SCRATCH_NUM; s++) {
if (strcmp(reg->name, xtensa->scratch_ars[s].chrval) == 0) {
LOG_DEBUG("Scratch reg %s [0x%08" PRIx32 "] set from gdb", reg->name,
buf_get_u32(reg->value, 0, 32));
LOG_DEBUG("scratch_ars mapping: a3/%s, a4/%s",
xtensa->scratch_ars[XT_AR_SCRATCH_AR3].chrval,
xtensa->scratch_ars[XT_AR_SCRATCH_AR4].chrval);
xtensa->scratch_ars[s].intval = true;
break;
}
}
}
reg->dirty = true;
reg->valid = true;
return ERROR_OK;
}
static const struct reg_arch_type xtensa_reg_type = {
.get = xtensa_core_reg_get,
.set = xtensa_core_reg_set,
};
/* Convert a register index that's indexed relative to windowbase, to the real address. */
static enum xtensa_reg_id xtensa_windowbase_offset_to_canonical(struct xtensa *xtensa,
enum xtensa_reg_id reg_idx,
int windowbase)
{
unsigned int idx;
if (reg_idx >= XT_REG_IDX_AR0 && reg_idx <= XT_REG_IDX_ARLAST) {
idx = reg_idx - XT_REG_IDX_AR0;
} else if (reg_idx >= XT_REG_IDX_A0 && reg_idx <= XT_REG_IDX_A15) {
idx = reg_idx - XT_REG_IDX_A0;
} else {
LOG_ERROR("Error: can't convert register %d to non-windowbased register!", reg_idx);
return -1;
}
/* Each windowbase value represents 4 registers on LX and 8 on NX */
int base_inc = (xtensa->core_config->core_type == XT_LX) ? 4 : 8;
return ((idx + windowbase * base_inc) & (xtensa->core_config->aregs_num - 1)) + XT_REG_IDX_AR0;
}
static enum xtensa_reg_id xtensa_canonical_to_windowbase_offset(struct xtensa *xtensa,
enum xtensa_reg_id reg_idx,
int windowbase)
{
return xtensa_windowbase_offset_to_canonical(xtensa, reg_idx, -windowbase);
}
static void xtensa_mark_register_dirty(struct xtensa *xtensa, enum xtensa_reg_id reg_idx)
{
struct reg *reg_list = xtensa->core_cache->reg_list;
reg_list[reg_idx].dirty = true;
}
static void xtensa_queue_exec_ins(struct xtensa *xtensa, uint32_t ins)
{
xtensa_queue_dbg_reg_write(xtensa, XDMREG_DIR0EXEC, ins);
}
static void xtensa_queue_exec_ins_wide(struct xtensa *xtensa, uint8_t *ops, uint8_t oplen)
{
const int max_oplen = 64; /* 8 DIRx regs: max width 64B */
if ((oplen > 0) && (oplen <= max_oplen)) {
uint8_t ops_padded[max_oplen];
memcpy(ops_padded, ops, oplen);
memset(ops_padded + oplen, 0, max_oplen - oplen);
unsigned int oplenw = DIV_ROUND_UP(oplen, sizeof(uint32_t));
for (int32_t i = oplenw - 1; i > 0; i--)
xtensa_queue_dbg_reg_write(xtensa,
XDMREG_DIR0 + i,
target_buffer_get_u32(xtensa->target, &ops_padded[sizeof(uint32_t)*i]));
/* Write DIR0EXEC last */
xtensa_queue_dbg_reg_write(xtensa,
XDMREG_DIR0EXEC,
target_buffer_get_u32(xtensa->target, &ops_padded[0]));
}
}
static int xtensa_queue_pwr_reg_write(struct xtensa *xtensa, unsigned int reg, uint32_t data)
{
struct xtensa_debug_module *dm = &xtensa->dbg_mod;
return dm->pwr_ops->queue_reg_write(dm, reg, data);
}
/* NOTE: Assumes A3 has already been saved */
static int xtensa_window_state_save(struct target *target, uint32_t *woe)
{
struct xtensa *xtensa = target_to_xtensa(target);
unsigned int woe_sr = (xtensa->core_config->core_type == XT_LX) ? XT_SR_PS : XT_SR_WB;
uint32_t woe_dis;
uint8_t woe_buf[4];
if (xtensa->core_config->windowed) {
/* Save PS (LX) or WB (NX) and disable window overflow exceptions prior to AR save */
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, woe_sr, XT_REG_A3));
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3));
xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, woe_buf);
int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK) {
LOG_TARGET_ERROR(target, "Failed to read %s (%d)!",
(woe_sr == XT_SR_PS) ? "PS" : "WB", res);
return res;
}
xtensa_core_status_check(target);
*woe = buf_get_u32(woe_buf, 0, 32);
woe_dis = *woe & ~((woe_sr == XT_SR_PS) ? XT_PS_WOE_MSK : XT_WB_S_MSK);
LOG_TARGET_DEBUG(target, "Clearing %s (0x%08" PRIx32 " -> 0x%08" PRIx32 ")",
(woe_sr == XT_SR_PS) ? "PS.WOE" : "WB.S", *woe, woe_dis);
xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, woe_dis);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, woe_sr, XT_REG_A3));
}
return ERROR_OK;
}
/* NOTE: Assumes A3 has already been saved */
static void xtensa_window_state_restore(struct target *target, uint32_t woe)
{
struct xtensa *xtensa = target_to_xtensa(target);
unsigned int woe_sr = (xtensa->core_config->core_type == XT_LX) ? XT_SR_PS : XT_SR_WB;
if (xtensa->core_config->windowed) {
/* Restore window overflow exception state */
xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, woe);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, woe_sr, XT_REG_A3));
LOG_TARGET_DEBUG(target, "Restored %s (0x%08" PRIx32 ")",
(woe_sr == XT_SR_PS) ? "PS.WOE" : "WB", woe);
}
}
static bool xtensa_reg_is_readable(int flags, int cpenable)
{
if (flags & XT_REGF_NOREAD)
return false;
if ((flags & XT_REGF_COPROC0) && (cpenable & BIT(0)) == 0)
return false;
return true;
}
static bool xtensa_scratch_regs_fixup(struct xtensa *xtensa, struct reg *reg_list, int i, int j, int a_idx, int ar_idx)
{
int a_name = (a_idx == XT_AR_SCRATCH_A3) ? 3 : 4;
if (xtensa->scratch_ars[a_idx].intval && !xtensa->scratch_ars[ar_idx].intval) {
LOG_DEBUG("AR conflict: a%d -> ar%d", a_name, j - XT_REG_IDX_AR0);
memcpy(reg_list[j].value, reg_list[i].value, sizeof(xtensa_reg_val_t));
} else {
LOG_DEBUG("AR conflict: ar%d -> a%d", j - XT_REG_IDX_AR0, a_name);
memcpy(reg_list[i].value, reg_list[j].value, sizeof(xtensa_reg_val_t));
}
return xtensa->scratch_ars[a_idx].intval && xtensa->scratch_ars[ar_idx].intval;
}
static int xtensa_write_dirty_registers(struct target *target)
{
struct xtensa *xtensa = target_to_xtensa(target);
int res;
xtensa_reg_val_t regval, windowbase = 0;
bool scratch_reg_dirty = false, delay_cpenable = false;
struct reg *reg_list = xtensa->core_cache->reg_list;
unsigned int reg_list_size = xtensa->core_cache->num_regs;
bool preserve_a3 = false;
uint8_t a3_buf[4];
xtensa_reg_val_t a3 = 0, woe;
unsigned int ms_idx = (xtensa->core_config->core_type == XT_NX) ?
xtensa->nx_reg_idx[XT_NX_REG_IDX_MS] : reg_list_size;
xtensa_reg_val_t ms = 0;
bool restore_ms = false;
LOG_TARGET_DEBUG(target, "start");
/* We need to write the dirty registers in the cache list back to the processor.
* Start by writing the SFR/user registers. */
for (unsigned int i = 0; i < reg_list_size; i++) {
struct xtensa_reg_desc *rlist = (i < XT_NUM_REGS) ? xtensa_regs : xtensa->optregs;
unsigned int ridx = (i < XT_NUM_REGS) ? i : i - XT_NUM_REGS;
if (reg_list[i].dirty) {
if (rlist[ridx].type == XT_REG_SPECIAL ||
rlist[ridx].type == XT_REG_USER ||
rlist[ridx].type == XT_REG_FR) {
scratch_reg_dirty = true;
if (i == XT_REG_IDX_CPENABLE) {
delay_cpenable = true;
continue;
}
regval = xtensa_reg_get(target, i);
LOG_TARGET_DEBUG(target, "Writing back reg %s (%d) val %08" PRIX32,
reg_list[i].name,
rlist[ridx].reg_num,
regval);
xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, regval);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
if (reg_list[i].exist) {
unsigned int reg_num = rlist[ridx].reg_num;
if (rlist[ridx].type == XT_REG_USER) {
xtensa_queue_exec_ins(xtensa, XT_INS_WUR(xtensa, reg_num, XT_REG_A3));
} else if (rlist[ridx].type == XT_REG_FR) {
xtensa_queue_exec_ins(xtensa, XT_INS_WFR(xtensa, reg_num, XT_REG_A3));
} else {/*SFR */
if (reg_num == XT_PC_REG_NUM_VIRTUAL) {
if (xtensa->core_config->core_type == XT_LX) {
/* reg number of PC for debug interrupt depends on NDEBUGLEVEL */
reg_num = (XT_EPC_REG_NUM_BASE + xtensa->core_config->debug.irq_level);
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, reg_num, XT_REG_A3));
} else {
/* NX PC set through issuing a jump instruction */
xtensa_queue_exec_ins(xtensa, XT_INS_JX(xtensa, XT_REG_A3));
}
} else if (i == ms_idx) {
/* MS must be restored after ARs. This ensures ARs remain in correct
* order even for reversed register groups (overflow/underflow).
*/
ms = regval;
restore_ms = true;
LOG_TARGET_DEBUG(target, "Delaying MS write: 0x%x", ms);
} else {
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, reg_num, XT_REG_A3));
}
}
}
reg_list[i].dirty = false;
}
}
}
if (scratch_reg_dirty)
xtensa_mark_register_dirty(xtensa, XT_REG_IDX_A3);
if (delay_cpenable) {
regval = xtensa_reg_get(target, XT_REG_IDX_CPENABLE);
LOG_TARGET_DEBUG(target, "Writing back reg cpenable (224) val %08" PRIX32, regval);
xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, regval);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa,
xtensa_regs[XT_REG_IDX_CPENABLE].reg_num,
XT_REG_A3));
reg_list[XT_REG_IDX_CPENABLE].dirty = false;
}
preserve_a3 = (xtensa->core_config->windowed) || (xtensa->core_config->core_type == XT_NX);
if (preserve_a3) {
/* Save (windowed) A3 for scratch use */
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, XT_SR_DDR, XT_REG_A3));
xtensa_queue_dbg_reg_read(xtensa, XDMREG_DDR, a3_buf);
res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK)
return res;
xtensa_core_status_check(target);
a3 = buf_get_u32(a3_buf, 0, 32);
}
if (xtensa->core_config->windowed) {
res = xtensa_window_state_save(target, &woe);
if (res != ERROR_OK)
return res;
/* Grab the windowbase, we need it. */
uint32_t wb_idx = (xtensa->core_config->core_type == XT_LX) ?
XT_REG_IDX_WINDOWBASE : xtensa->nx_reg_idx[XT_NX_REG_IDX_WB];
windowbase = xtensa_reg_get(target, wb_idx);
if (xtensa->core_config->core_type == XT_NX)
windowbase = (windowbase & XT_WB_P_MSK) >> XT_WB_P_SHIFT;
/* Check if there are mismatches between the ARx and corresponding Ax registers.
* When the user sets a register on a windowed config, xt-gdb may set the ARx
* register directly. Thus we take ARx as priority over Ax if both are dirty
* and it's unclear if the user set one over the other explicitly.
*/
for (unsigned int i = XT_REG_IDX_A0; i <= XT_REG_IDX_A15; i++) {
unsigned int j = xtensa_windowbase_offset_to_canonical(xtensa, i, windowbase);
if (reg_list[i].dirty && reg_list[j].dirty) {
if (memcmp(reg_list[i].value, reg_list[j].value, sizeof(xtensa_reg_val_t)) != 0) {
bool show_warning = true;
if (i == XT_REG_IDX_A3)
show_warning = xtensa_scratch_regs_fixup(xtensa,
reg_list, i, j, XT_AR_SCRATCH_A3, XT_AR_SCRATCH_AR3);
else if (i == XT_REG_IDX_A4)
show_warning = xtensa_scratch_regs_fixup(xtensa,
reg_list, i, j, XT_AR_SCRATCH_A4, XT_AR_SCRATCH_AR4);
if (show_warning)
LOG_WARNING(
"Warning: Both A%d [0x%08" PRIx32
"] as well as its underlying physical register "
"(AR%d) [0x%08" PRIx32 "] are dirty and differ in value",
i - XT_REG_IDX_A0,
buf_get_u32(reg_list[i].value, 0, 32),
j - XT_REG_IDX_AR0,
buf_get_u32(reg_list[j].value, 0, 32));
}
}
}
}
/* Write A0-A16. */
for (unsigned int i = 0; i < 16; i++) {
if (reg_list[XT_REG_IDX_A0 + i].dirty) {
regval = xtensa_reg_get(target, XT_REG_IDX_A0 + i);
LOG_TARGET_DEBUG(target, "Writing back reg %s value %08" PRIX32 ", num =%i",
xtensa_regs[XT_REG_IDX_A0 + i].name,
regval,
xtensa_regs[XT_REG_IDX_A0 + i].reg_num);
xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, regval);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, i));
reg_list[XT_REG_IDX_A0 + i].dirty = false;
if (i == 3) {
/* Avoid stomping A3 during restore at end of function */
a3 = regval;
}
}
}
if (xtensa->core_config->windowed) {
/* Now write AR registers */
for (unsigned int j = 0; j < XT_REG_IDX_ARLAST; j += 16) {
/* Write the 16 registers we can see */
for (unsigned int i = 0; i < 16; i++) {
if (i + j < xtensa->core_config->aregs_num) {
enum xtensa_reg_id realadr =
xtensa_windowbase_offset_to_canonical(xtensa, XT_REG_IDX_AR0 + i + j,
windowbase);
/* Write back any dirty un-windowed registers */
if (reg_list[realadr].dirty) {
regval = xtensa_reg_get(target, realadr);
LOG_TARGET_DEBUG(
target,
"Writing back reg %s value %08" PRIX32 ", num =%i",
xtensa_regs[realadr].name,
regval,
xtensa_regs[realadr].reg_num);
xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, regval);
xtensa_queue_exec_ins(xtensa,
XT_INS_RSR(xtensa, XT_SR_DDR,
xtensa_regs[XT_REG_IDX_AR0 + i].reg_num));
reg_list[realadr].dirty = false;
if ((i + j) == 3)
/* Avoid stomping AR during A3 restore at end of function */
a3 = regval;
}
}
}
/* Now rotate the window so we'll see the next 16 registers. The final rotate
* will wraparound, leaving us in the state we were.
* Each ROTW rotates 4 registers on LX and 8 on NX */
int rotw_arg = (xtensa->core_config->core_type == XT_LX) ? 4 : 2;
xtensa_queue_exec_ins(xtensa, XT_INS_ROTW(xtensa, rotw_arg));
}
xtensa_window_state_restore(target, woe);
for (enum xtensa_ar_scratch_set_e s = 0; s < XT_AR_SCRATCH_NUM; s++)
xtensa->scratch_ars[s].intval = false;
}
if (restore_ms) {
uint32_t ms_regno = xtensa->optregs[ms_idx - XT_NUM_REGS].reg_num;
xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, ms);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
xtensa_queue_exec_ins(xtensa, XT_INS_WSR(xtensa, ms_regno, XT_REG_A3));
LOG_TARGET_DEBUG(target, "Delayed MS (0x%x) write complete: 0x%x", ms_regno, ms);
}
if (preserve_a3) {
xtensa_queue_dbg_reg_write(xtensa, XDMREG_DDR, a3);
xtensa_queue_exec_ins(xtensa, XT_INS_RSR(xtensa, XT_SR_DDR, XT_REG_A3));
}
res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
xtensa_core_status_check(target);
return res;
}
static inline bool xtensa_is_stopped(struct target *target)
{
struct xtensa *xtensa = target_to_xtensa(target);
return xtensa->dbg_mod.core_status.dsr & OCDDSR_STOPPED;
}
int xtensa_examine(struct target *target)
{
struct xtensa *xtensa = target_to_xtensa(target);
unsigned int cmd = PWRCTL_DEBUGWAKEUP(xtensa) | PWRCTL_MEMWAKEUP(xtensa) | PWRCTL_COREWAKEUP(xtensa);
LOG_DEBUG("coreid = %d", target->coreid);
if (xtensa->core_config->core_type == XT_UNDEF) {
LOG_ERROR("XTensa core not configured; is xtensa-core-openocd.cfg missing?");
return ERROR_FAIL;
}
xtensa_queue_pwr_reg_write(xtensa, XDMREG_PWRCTL, cmd);
xtensa_queue_pwr_reg_write(xtensa, XDMREG_PWRCTL, cmd | PWRCTL_JTAGDEBUGUSE(xtensa));
xtensa_dm_queue_enable(&xtensa->dbg_mod);
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
if (res != ERROR_OK)
return res;
if (!xtensa_dm_is_online(&xtensa->dbg_mod)) {
LOG_ERROR("Unexpected OCD_ID = %08" PRIx32, xtensa->dbg_mod.device_id);
return ERROR_TARGET_FAILURE;
}
LOG_DEBUG("OCD_ID = %08" PRIx32, xtensa->dbg_mod.device_id);
target_set_examined(target);
xtensa_smpbreak_write(xtensa, xtensa->smp_break);
return ERROR_OK;
}
int xtensa_wakeup(struct target *target)
{
struct xtensa *xtensa = target_to_xtensa(target);
unsigned int cmd = PWRCTL_DEBUGWAKEUP(xtensa) | PWRCTL_MEMWAKEUP(xtensa) | PWRCTL_COREWAKEUP(xtensa);
if (xtensa->reset_asserted)
cmd |= PWRCTL_CORERESET(xtensa);
xtensa_queue_pwr_reg_write(xtensa, XDMREG_PWRCTL, cmd);
/* TODO: can we join this with the write above? */
xtensa_queue_pwr_reg_write(xtensa, XDMREG_PWRCTL, cmd | PWRCTL_JTAGDEBUGUSE(xtensa));
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
return xtensa_dm_queue_execute(&xtensa->dbg_mod);
}
int xtensa_smpbreak_write(struct xtensa *xtensa, uint32_t set)
{
uint32_t dsr_data = 0x00110000;
uint32_t clear = (set | OCDDCR_ENABLEOCD) ^
(OCDDCR_BREAKINEN | OCDDCR_BREAKOUTEN | OCDDCR_RUNSTALLINEN |
OCDDCR_DEBUGMODEOUTEN | OCDDCR_ENABLEOCD);
LOG_TARGET_DEBUG(xtensa->target, "write smpbreak set=0x%" PRIx32 " clear=0x%" PRIx32, set, clear);
xtensa_queue_dbg_reg_write(xtensa, XDMREG_DCRSET, set | OCDDCR_ENABLEOCD);
xtensa_queue_dbg_reg_write(xtensa, XDMREG_DCRCLR, clear);
xtensa_queue_dbg_reg_write(xtensa, XDMREG_DSR, dsr_data);
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
return xtensa_dm_queue_execute(&xtensa->dbg_mod);
}
int xtensa_smpbreak_set(struct target *target, uint32_t set)
{
struct xtensa *xtensa = target_to_xtensa(target);
int res = ERROR_OK;
xtensa->smp_break = set;
if (target_was_examined(target))
res = xtensa_smpbreak_write(xtensa, xtensa->smp_break);
LOG_TARGET_DEBUG(target, "set smpbreak=%" PRIx32 ", state=%i", set, target->state);
return res;
}
int xtensa_smpbreak_read(struct xtensa *xtensa, uint32_t *val)
{
uint8_t dcr_buf[sizeof(uint32_t)];
xtensa_queue_dbg_reg_read(xtensa, XDMREG_DCRSET, dcr_buf);
xtensa_dm_queue_tdi_idle(&xtensa->dbg_mod);
int res = xtensa_dm_queue_execute(&xtensa->dbg_mod);
*val = buf_get_u32(dcr_buf, 0, 32);
return res;
}
int xtensa_smpbreak_get(struct target *target, uint32_t *val)
{
struct xtensa *xtensa = target_to_xtensa(target);
*val = xtensa->smp_break;
return ERROR_OK;
}
static inline xtensa_reg_val_t xtensa_reg_get_value(struct reg *reg)
{
return buf_get_u32(reg->value, 0, 32);
}
static inline void xtensa_reg_set_value(struct reg *reg, xtensa_reg_val_t value)
{
buf_set_u32(reg->value, 0, 32, value);
reg->dirty = true;
}
static int xtensa_imprecise_exception_occurred(struct target *target)
{
struct xtensa *xtensa = target_to_xtensa(target);
for (enum xtensa_nx_reg_idx idx = XT_NX_REG_IDX_IEVEC; idx <= XT_NX_REG_IDX_MESR; idx++) {
enum xtensa_reg_id ridx = xtensa->nx_reg_idx[idx];
if (xtensa->nx_reg_idx[idx]) {
xtensa_reg_val_t reg = xtensa_reg_get(target, xtensa->nx_reg_idx[idx]);
if (reg & XT_IMPR_EXC_MSK) {
LOG_TARGET_DEBUG(target, "Imprecise exception: %s: 0x%x",
xtensa->core_cache->reg_list[ridx].name, reg);
return true;
}
}
}
return false;
}
static void xtensa_imprecise_exception_clear(struct target *target)
{
struct xtensa *xtensa = target_to_xtensa(target);
for (enum xtensa_nx_reg_idx idx = XT_NX_REG_IDX_IEVEC; idx <= XT_NX_REG_IDX_MESRCLR; idx++) {
enum xtensa_reg_id ridx = xtensa->nx_reg_idx[idx];
if (ridx && idx != XT_NX_REG_IDX_MESR) {
xtensa_reg_val_t value = (idx == XT_NX_REG_IDX_MESRCLR) ? XT_MESRCLR_IMPR_EXC_MSK : 0;
xtensa_reg_set(target, ridx, value);
LOG_TARGET_DEBUG(target, "Imprecise exception: clearing %s (0x%x)",
xtensa->core_cache->reg_list[ridx].name, value);
}
}
}
int xtensa_core_status_check(struct target *target)
{
struct xtensa *xtensa = target_to_xtensa(target);
int res, needclear = 0, needimprclear = 0;
xtensa_dm_core_status_read(&xtensa->dbg_mod);
xtensa_dsr_t dsr = xtensa_dm_core_status_get(&xtensa->dbg_mod);
LOG_TARGET_DEBUG(target, "DSR (%08" PRIX32 ")", dsr);
if (dsr & OCDDSR_EXECBUSY) {
if (!xtensa->suppress_dsr_errors)
LOG_TARGET_ERROR(target, "DSR (%08" PRIX32 ") indicates target still busy!", dsr);
needclear = 1;
}
if (dsr & OCDDSR_EXECEXCEPTION) {
if (!xtensa->suppress_dsr_errors)
LOG_TARGET_ERROR(target,
"DSR (%08" PRIX32 ") indicates DIR instruction generated an exception!",
dsr);
needclear = 1;
}
if (dsr & OCDDSR_EXECOVERRUN) {
if (!xtensa->suppress_dsr_errors)
LOG_TARGET_ERROR(target,
"DSR (%08" PRIX32 ") indicates DIR instruction generated an overrun!",
dsr);
needclear = 1;
}
if (xtensa->core_config->core_type == XT_NX && (xtensa_imprecise_exception_occurred(target))) {
if (!xtensa->suppress_dsr_errors)
LOG_TARGET_ERROR(target,
"%s: Imprecise exception occurred!", target_name(target));
needclear = 1;
needimprclear = 1;
}
if (needclear) {
res = xtensa_dm_core_status_clear(&xtensa->dbg_mod,
OCDDSR_EXECEXCEPTION | OCDDSR_EXECOVERRUN);
if (res != ERROR_OK && !xtensa->suppress_dsr_errors)
LOG_TARGET_ERROR(target, "clearing DSR failed!");
if (xtensa->core_config->core_type == XT_NX && needimprclear)
xtensa_imprecise_exception_clear(target);
return ERROR_FAIL;
}
return ERROR_OK;
}
xtensa_reg_val_t xtensa_reg_get(struct target *target, enum xtensa_reg_id reg_id)
{
struct xtensa *xtensa = target_to_xtensa(target);
struct reg *reg = &xtensa->core_cache->reg_list[reg_id];