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[DAG] Use legal shift amount type in DAGTypeLegalizer::JoinIntegers
Documentation for TargetLowering::getShiftAmountTy says that LegalTypes should generally be true during type legalization, so this patch does that. On AMDGPU the effect is that we use i32 (a sane type) instead of i64 (pointer sized type) for more shift amounts, which in turn allows more formation of rotates and funnel shifts pre-legalization. Differential Revision: https://reviews.llvm.org/D154960
1 parent 4936450 commit f7684d8

18 files changed

+637
-699
lines changed

‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1000,7 +1000,7 @@ SDValue DAGTypeLegalizer::JoinIntegers(SDValue Lo, SDValue Hi) {
10001000
EVT NVT = EVT::getIntegerVT(*DAG.getContext(),
10011001
LVT.getSizeInBits() + HVT.getSizeInBits());
10021002

1003-
EVT ShiftAmtVT = TLI.getShiftAmountTy(NVT, DAG.getDataLayout(), false);
1003+
EVT ShiftAmtVT = TLI.getShiftAmountTy(NVT, DAG.getDataLayout());
10041004
Lo = DAG.getNode(ISD::ZERO_EXTEND, dlLo, NVT, Lo);
10051005
Hi = DAG.getNode(ISD::ANY_EXTEND, dlHi, NVT, Hi);
10061006
Hi = DAG.getNode(ISD::SHL, dlHi, NVT, Hi,

‎llvm/lib/Target/AMDGPU/SIISelLowering.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -10415,6 +10415,9 @@ calculateByteProvider(const SDValue &Op, unsigned Index, unsigned Depth,
1041510415
return std::nullopt;
1041610416
}
1041710417

10418+
case ISD::BSWAP:
10419+
return calculateByteProvider(Op->getOperand(0), BitWidth / 8 - Index - 1,
10420+
Depth + 1, StartingIndex);
1041810421
default: {
1041910422
return std::nullopt;
1042010423
}

‎llvm/test/CodeGen/AMDGPU/bswap.ll

Lines changed: 32 additions & 37 deletions
Original file line numberDiff line numberDiff line change
@@ -602,17 +602,15 @@ define <2 x i16> @v_bswap_v2i16(<2 x i16> %src) {
602602
; SI-LABEL: v_bswap_v2i16:
603603
; SI: ; %bb.0:
604604
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
605-
; SI-NEXT: v_alignbit_b32 v2, v1, v1, 8
606-
; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24
607-
; SI-NEXT: s_mov_b32 s4, 0xff00ff
608-
; SI-NEXT: v_alignbit_b32 v3, v0, v0, 8
605+
; SI-NEXT: v_alignbit_b32 v2, v0, v0, 8
609606
; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24
610-
; SI-NEXT: v_bfi_b32 v1, s4, v1, v2
611-
; SI-NEXT: v_bfi_b32 v0, s4, v0, v3
612-
; SI-NEXT: v_and_b32_e32 v2, 0xffff0000, v1
613-
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
614-
; SI-NEXT: v_or_b32_e32 v0, v0, v2
607+
; SI-NEXT: s_mov_b32 s4, 0xff00ff
608+
; SI-NEXT: v_alignbit_b32 v3, v1, v1, 8
609+
; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24
610+
; SI-NEXT: v_bfi_b32 v0, s4, v0, v2
611+
; SI-NEXT: v_bfi_b32 v1, s4, v1, v3
615612
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
613+
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
616614
; SI-NEXT: s_setpc_b64 s[30:31]
617615
;
618616
; VI-LABEL: v_bswap_v2i16:
@@ -635,21 +633,20 @@ define <3 x i16> @v_bswap_v3i16(<3 x i16> %src) {
635633
; SI-LABEL: v_bswap_v3i16:
636634
; SI: ; %bb.0:
637635
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
638-
; SI-NEXT: v_alignbit_b32 v3, v1, v1, 8
639-
; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24
640-
; SI-NEXT: s_mov_b32 s4, 0xff00ff
641-
; SI-NEXT: v_alignbit_b32 v4, v0, v0, 8
636+
; SI-NEXT: v_alignbit_b32 v3, v0, v0, 8
642637
; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24
638+
; SI-NEXT: s_mov_b32 s4, 0xff00ff
639+
; SI-NEXT: v_alignbit_b32 v4, v1, v1, 8
640+
; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24
643641
; SI-NEXT: v_alignbit_b32 v5, v2, v2, 8
644642
; SI-NEXT: v_alignbit_b32 v2, v2, v2, 24
645-
; SI-NEXT: v_bfi_b32 v1, s4, v1, v3
646-
; SI-NEXT: v_bfi_b32 v0, s4, v0, v4
643+
; SI-NEXT: v_bfi_b32 v0, s4, v0, v3
644+
; SI-NEXT: v_bfi_b32 v1, s4, v1, v4
647645
; SI-NEXT: v_bfi_b32 v2, s4, v2, v5
648-
; SI-NEXT: v_and_b32_e32 v3, 0xffff0000, v1
649-
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
646+
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
647+
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
650648
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
651-
; SI-NEXT: v_or_b32_e32 v0, v0, v3
652-
; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
649+
; SI-NEXT: v_alignbit_b32 v1, v2, v0, 16
653650
; SI-NEXT: s_setpc_b64 s[30:31]
654651
;
655652
; VI-LABEL: v_bswap_v3i16:
@@ -674,27 +671,25 @@ define <4 x i16> @v_bswap_v4i16(<4 x i16> %src) {
674671
; SI-LABEL: v_bswap_v4i16:
675672
; SI: ; %bb.0:
676673
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
677-
; SI-NEXT: v_alignbit_b32 v4, v1, v1, 8
678-
; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24
674+
; SI-NEXT: v_alignbit_b32 v4, v2, v2, 8
675+
; SI-NEXT: v_alignbit_b32 v2, v2, v2, 24
679676
; SI-NEXT: s_mov_b32 s4, 0xff00ff
680-
; SI-NEXT: v_alignbit_b32 v5, v0, v0, 8
681-
; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24
682-
; SI-NEXT: v_alignbit_b32 v6, v3, v3, 8
677+
; SI-NEXT: v_alignbit_b32 v5, v3, v3, 8
683678
; SI-NEXT: v_alignbit_b32 v3, v3, v3, 24
684-
; SI-NEXT: v_alignbit_b32 v7, v2, v2, 8
685-
; SI-NEXT: v_alignbit_b32 v2, v2, v2, 24
686-
; SI-NEXT: v_bfi_b32 v1, s4, v1, v4
687-
; SI-NEXT: v_bfi_b32 v0, s4, v0, v5
688-
; SI-NEXT: v_bfi_b32 v3, s4, v3, v6
689-
; SI-NEXT: v_bfi_b32 v2, s4, v2, v7
690-
; SI-NEXT: v_and_b32_e32 v4, 0xffff0000, v1
691-
; SI-NEXT: v_lshrrev_b32_e32 v0, 16, v0
692-
; SI-NEXT: v_and_b32_e32 v5, 0xffff0000, v3
693-
; SI-NEXT: v_lshrrev_b32_e32 v2, 16, v2
694-
; SI-NEXT: v_or_b32_e32 v0, v0, v4
695-
; SI-NEXT: v_or_b32_e32 v2, v2, v5
696-
; SI-NEXT: v_alignbit_b32 v1, v2, v1, 16
679+
; SI-NEXT: v_alignbit_b32 v6, v0, v0, 8
680+
; SI-NEXT: v_alignbit_b32 v0, v0, v0, 24
681+
; SI-NEXT: v_alignbit_b32 v7, v1, v1, 8
682+
; SI-NEXT: v_alignbit_b32 v1, v1, v1, 24
683+
; SI-NEXT: v_bfi_b32 v2, s4, v2, v4
684+
; SI-NEXT: v_bfi_b32 v3, s4, v3, v5
685+
; SI-NEXT: v_bfi_b32 v0, s4, v0, v6
686+
; SI-NEXT: v_bfi_b32 v1, s4, v1, v7
697687
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v3
688+
; SI-NEXT: v_lshrrev_b32_e32 v1, 16, v1
689+
; SI-NEXT: v_alignbit_b32 v2, v3, v2, 16
690+
; SI-NEXT: v_alignbit_b32 v0, v1, v0, 16
691+
; SI-NEXT: v_alignbit_b32 v1, v2, v0, 16
692+
; SI-NEXT: v_lshrrev_b32_e32 v3, 16, v2
698693
; SI-NEXT: s_setpc_b64 s[30:31]
699694
;
700695
; VI-LABEL: v_bswap_v4i16:

‎llvm/test/CodeGen/AMDGPU/build_vector.ll

Lines changed: 1 addition & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -71,10 +71,7 @@ entry:
7171
; R600-NOT: MOV
7272
; GFX6: s_mov_b32 s3, 0xf000
7373
; GFX6: s_waitcnt lgkmcnt(0)
74-
; GFX6: s_lshr_b32 s2, s2, 16
75-
; GFX6: s_or_b32 s4, s2, 0x50000
76-
; GFX6: s_mov_b32 s2, -1
77-
; GFX6: v_mov_b32_e32 v0, s4
74+
; GFX6: v_alignbit_b32 v0, 5, s4, 16
7875
; GFX6: buffer_store_dword v0, off, s[0:3], 0
7976
; GFX8: s_mov_b32 s3, 0xf000
8077
; GFX8: s_mov_b32 s2, -1

‎llvm/test/CodeGen/AMDGPU/cvt_f32_ubyte.ll

Lines changed: 47 additions & 50 deletions
Original file line numberDiff line numberDiff line change
@@ -1392,27 +1392,29 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_unaligned_multiuse(<4 x float> add
13921392
; SI-NEXT: s_waitcnt lgkmcnt(0)
13931393
; SI-NEXT: s_mov_b64 s[12:13], s[4:5]
13941394
; SI-NEXT: buffer_load_ubyte v2, v[0:1], s[12:15], 0 addr64 offset:3
1395-
; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[12:15], 0 addr64 offset:2
1396-
; SI-NEXT: s_mov_b64 s[12:13], s[6:7]
13971395
; SI-NEXT: buffer_load_ubyte v4, v[0:1], s[12:15], 0 addr64 offset:2
1396+
; SI-NEXT: s_mov_b64 s[12:13], s[6:7]
1397+
; SI-NEXT: buffer_load_ubyte v3, v[0:1], s[12:15], 0 addr64 offset:2
13981398
; SI-NEXT: s_mov_b32 s10, -1
13991399
; SI-NEXT: s_mov_b32 s8, s2
14001400
; SI-NEXT: s_mov_b32 s9, s3
14011401
; SI-NEXT: s_mov_b32 s2, s10
14021402
; SI-NEXT: s_mov_b32 s3, s11
14031403
; SI-NEXT: s_waitcnt vmcnt(2)
1404-
; SI-NEXT: v_lshlrev_b32_e32 v5, 24, v2
1404+
; SI-NEXT: v_lshlrev_b32_e32 v5, 8, v2
14051405
; SI-NEXT: s_waitcnt vmcnt(1)
1406-
; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v3
1407-
; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v3
1406+
; SI-NEXT: v_lshlrev_b32_e32 v6, 8, v4
1407+
; SI-NEXT: v_or_b32_e32 v5, v5, v4
1408+
; SI-NEXT: v_cvt_f32_ubyte0_e32 v1, v4
14081409
; SI-NEXT: s_waitcnt vmcnt(0)
1409-
; SI-NEXT: v_or_b32_e32 v6, v4, v6
1410+
; SI-NEXT: v_or_b32_e32 v6, v3, v6
1411+
; SI-NEXT: v_lshlrev_b32_e32 v5, 16, v5
14101412
; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v2
1411-
; SI-NEXT: v_alignbit_b32 v5, v3, v5, 24
1412-
; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v4
1413+
; SI-NEXT: v_cvt_f32_ubyte0_e32 v2, v3
14131414
; SI-NEXT: v_mov_b32_e32 v3, v1
1414-
; SI-NEXT: v_lshlrev_b32_e32 v4, 16, v6
1415-
; SI-NEXT: v_or_b32_e32 v4, v5, v4
1415+
; SI-NEXT: v_lshlrev_b32_e32 v6, 16, v6
1416+
; SI-NEXT: v_alignbit_b32 v4, v4, v5, 24
1417+
; SI-NEXT: v_or_b32_e32 v4, v4, v6
14161418
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
14171419
; SI-NEXT: buffer_store_dword v4, off, s[8:11], 0
14181420
; SI-NEXT: s_endpgm
@@ -1572,23 +1574,23 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %o
15721574
; SI-NEXT: s_mov_b32 s7, s3
15731575
; SI-NEXT: s_waitcnt vmcnt(0)
15741576
; SI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
1577+
; SI-NEXT: v_and_b32_e32 v6, 0xff00, v4
15751578
; SI-NEXT: v_cvt_f32_ubyte3_e32 v3, v4
15761579
; SI-NEXT: v_cvt_f32_ubyte2_e32 v2, v4
15771580
; SI-NEXT: v_cvt_f32_ubyte1_e32 v1, v4
15781581
; SI-NEXT: v_cvt_f32_ubyte0_e32 v0, v4
1579-
; SI-NEXT: v_add_i32_e32 v7, vcc, 9, v4
1580-
; SI-NEXT: v_and_b32_e32 v6, 0xff00, v4
1582+
; SI-NEXT: v_add_i32_e32 v4, vcc, 9, v4
15811583
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
15821584
; SI-NEXT: s_waitcnt expcnt(0)
1583-
; SI-NEXT: v_and_b32_e32 v0, 0xff, v7
1584-
; SI-NEXT: v_add_i32_e32 v1, vcc, 9, v5
1585+
; SI-NEXT: v_and_b32_e32 v0, 0xff, v4
1586+
; SI-NEXT: v_add_i32_e32 v2, vcc, 9, v5
1587+
; SI-NEXT: v_and_b32_e32 v1, 0xff00, v5
15851588
; SI-NEXT: v_or_b32_e32 v0, v6, v0
1586-
; SI-NEXT: v_and_b32_e32 v1, 0xff, v1
1587-
; SI-NEXT: v_and_b32_e32 v4, 0xff000000, v4
1589+
; SI-NEXT: v_and_b32_e32 v2, 0xff, v2
15881590
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x900, v0
1589-
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
1591+
; SI-NEXT: v_or_b32_e32 v1, v1, v2
15901592
; SI-NEXT: v_and_b32_e32 v0, 0xffff, v0
1591-
; SI-NEXT: v_or_b32_e32 v1, v4, v1
1593+
; SI-NEXT: v_lshlrev_b32_e32 v1, 16, v1
15921594
; SI-NEXT: v_or_b32_e32 v0, v1, v0
15931595
; SI-NEXT: v_add_i32_e32 v0, vcc, 0x9000000, v0
15941596
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
@@ -1600,7 +1602,6 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %o
16001602
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
16011603
; VI-NEXT: s_mov_b32 s7, 0xf000
16021604
; VI-NEXT: s_mov_b32 s6, -1
1603-
; VI-NEXT: v_mov_b32_e32 v5, 9
16041605
; VI-NEXT: s_waitcnt lgkmcnt(0)
16051606
; VI-NEXT: v_mov_b32_e32 v1, s3
16061607
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
@@ -1613,19 +1614,19 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %o
16131614
; VI-NEXT: s_mov_b32 s2, s6
16141615
; VI-NEXT: s_mov_b32 s3, s7
16151616
; VI-NEXT: s_waitcnt vmcnt(0)
1616-
; VI-NEXT: v_lshrrev_b32_e32 v6, 24, v4
1617+
; VI-NEXT: v_lshrrev_b32_e32 v5, 16, v4
16171618
; VI-NEXT: v_cvt_f32_ubyte3_e32 v3, v4
16181619
; VI-NEXT: v_cvt_f32_ubyte2_e32 v2, v4
16191620
; VI-NEXT: v_cvt_f32_ubyte1_e32 v1, v4
16201621
; VI-NEXT: v_cvt_f32_ubyte0_e32 v0, v4
1621-
; VI-NEXT: v_and_b32_e32 v7, 0xffffff00, v4
1622-
; VI-NEXT: v_add_u16_e32 v8, 9, v4
1623-
; VI-NEXT: v_add_u16_sdwa v4, v4, v5 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1622+
; VI-NEXT: v_and_b32_e32 v6, 0xffffff00, v4
1623+
; VI-NEXT: v_add_u16_e32 v4, 9, v4
16241624
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
16251625
; VI-NEXT: s_nop 0
1626-
; VI-NEXT: v_lshlrev_b16_e32 v1, 8, v6
1627-
; VI-NEXT: v_or_b32_sdwa v0, v7, v8 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1628-
; VI-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1626+
; VI-NEXT: v_and_b32_e32 v1, 0xffffff00, v5
1627+
; VI-NEXT: v_add_u16_e32 v2, 9, v5
1628+
; VI-NEXT: v_or_b32_sdwa v0, v6, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1629+
; VI-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
16291630
; VI-NEXT: v_mov_b32_e32 v2, 0x900
16301631
; VI-NEXT: v_add_u16_e32 v0, 0x900, v0
16311632
; VI-NEXT: v_add_u16_sdwa v1, v1, v2 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
@@ -1637,18 +1638,17 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %o
16371638
; GFX10: ; %bb.0:
16381639
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
16391640
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
1640-
; GFX10-NEXT: v_mov_b32_e32 v1, 24
16411641
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
16421642
; GFX10-NEXT: global_load_dword v0, v0, s[2:3]
16431643
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
16441644
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
16451645
; GFX10-NEXT: s_waitcnt vmcnt(0)
1646-
; GFX10-NEXT: v_lshrrev_b32_e32 v2, 16, v0
1647-
; GFX10-NEXT: v_lshrrev_b32_sdwa v1, v1, v0 dst_sel:BYTE_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
1646+
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v0
16481647
; GFX10-NEXT: v_and_b32_e32 v3, 0xffffff00, v0
16491648
; GFX10-NEXT: v_add_nc_u16 v4, v0, 9
1650-
; GFX10-NEXT: v_add_nc_u16 v2, v2, 9
1651-
; GFX10-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1649+
; GFX10-NEXT: v_and_b32_e32 v2, 0xffffff00, v1
1650+
; GFX10-NEXT: v_add_nc_u16 v1, v1, 9
1651+
; GFX10-NEXT: v_or_b32_sdwa v1, v2, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
16521652
; GFX10-NEXT: v_or_b32_sdwa v2, v3, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
16531653
; GFX10-NEXT: v_mov_b32_e32 v4, 0
16541654
; GFX10-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
@@ -1669,26 +1669,25 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %o
16691669
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x34
16701670
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
16711671
; GFX9-NEXT: v_mov_b32_e32 v5, 0
1672-
; GFX9-NEXT: v_mov_b32_e32 v6, 9
16731672
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
16741673
; GFX9-NEXT: global_load_dword v4, v0, s[0:1]
16751674
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
16761675
; GFX9-NEXT: s_movk_i32 s4, 0x900
16771676
; GFX9-NEXT: s_waitcnt vmcnt(0)
1678-
; GFX9-NEXT: v_lshrrev_b32_e32 v7, 24, v4
1677+
; GFX9-NEXT: v_lshrrev_b32_e32 v6, 16, v4
16791678
; GFX9-NEXT: v_cvt_f32_ubyte3_e32 v3, v4
16801679
; GFX9-NEXT: v_cvt_f32_ubyte2_e32 v2, v4
16811680
; GFX9-NEXT: v_cvt_f32_ubyte1_e32 v1, v4
16821681
; GFX9-NEXT: v_cvt_f32_ubyte0_e32 v0, v4
1683-
; GFX9-NEXT: v_and_b32_e32 v8, 0xffffff00, v4
1684-
; GFX9-NEXT: v_add_u16_e32 v9, 9, v4
1685-
; GFX9-NEXT: v_add_u16_sdwa v4, v4, v6 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
1682+
; GFX9-NEXT: v_and_b32_e32 v7, 0xffffff00, v4
1683+
; GFX9-NEXT: v_add_u16_e32 v4, 9, v4
16861684
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
16871685
; GFX9-NEXT: global_store_dwordx4 v5, v[0:3], s[0:1]
16881686
; GFX9-NEXT: s_nop 0
1689-
; GFX9-NEXT: v_lshlrev_b16_e32 v1, 8, v7
1690-
; GFX9-NEXT: v_or_b32_sdwa v0, v8, v9 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1691-
; GFX9-NEXT: v_or_b32_sdwa v1, v1, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1687+
; GFX9-NEXT: v_and_b32_e32 v1, 0xffffff00, v6
1688+
; GFX9-NEXT: v_add_u16_e32 v2, 9, v6
1689+
; GFX9-NEXT: v_or_b32_sdwa v0, v7, v4 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
1690+
; GFX9-NEXT: v_or_b32_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:BYTE_0
16921691
; GFX9-NEXT: v_add_u16_e32 v0, 0x900, v0
16931692
; GFX9-NEXT: v_add_u16_sdwa v1, v1, s4 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:DWORD src1_sel:DWORD
16941693
; GFX9-NEXT: v_or_b32_e32 v0, v0, v1
@@ -1705,29 +1704,27 @@ define amdgpu_kernel void @load_v4i8_to_v4f32_2_uses(ptr addrspace(1) noalias %o
17051704
; GFX11-NEXT: s_waitcnt vmcnt(0)
17061705
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
17071706
; GFX11-NEXT: v_add_nc_u16 v2, v0, 9
1708-
; GFX11-NEXT: v_lshrrev_b32_e32 v3, 24, v0
17091707
; GFX11-NEXT: v_and_b32_e32 v4, 0xffffff00, v0
1710-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_4)
1711-
; GFX11-NEXT: v_add_nc_u16 v1, v1, 9
1708+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
1709+
; GFX11-NEXT: v_add_nc_u16 v3, v1, 9
17121710
; GFX11-NEXT: v_and_b32_e32 v2, 0xff, v2
1713-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_4) | instskip(NEXT) | instid1(VALU_DEP_3)
1714-
; GFX11-NEXT: v_lshlrev_b16 v3, 8, v3
1715-
; GFX11-NEXT: v_and_b32_e32 v1, 0xff, v1
1716-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
1711+
; GFX11-NEXT: v_and_b32_e32 v1, 0xffffff00, v1
1712+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
1713+
; GFX11-NEXT: v_and_b32_e32 v3, 0xff, v3
17171714
; GFX11-NEXT: v_or_b32_e32 v2, v4, v2
17181715
; GFX11-NEXT: v_mov_b32_e32 v4, 0
1719-
; GFX11-NEXT: v_or_b32_e32 v1, v3, v1
1720-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
1716+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
1717+
; GFX11-NEXT: v_or_b32_e32 v1, v1, v3
17211718
; GFX11-NEXT: v_add_nc_u16 v2, v2, 0x900
17221719
; GFX11-NEXT: v_cvt_f32_ubyte3_e32 v3, v0
1720+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
17231721
; GFX11-NEXT: v_add_nc_u16 v1, v1, 0x900
1724-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_3)
17251722
; GFX11-NEXT: v_and_b32_e32 v5, 0xffff, v2
17261723
; GFX11-NEXT: v_cvt_f32_ubyte2_e32 v2, v0
1724+
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_2) | instid1(VALU_DEP_3)
17271725
; GFX11-NEXT: v_lshlrev_b32_e32 v6, 16, v1
17281726
; GFX11-NEXT: v_cvt_f32_ubyte1_e32 v1, v0
17291727
; GFX11-NEXT: v_cvt_f32_ubyte0_e32 v0, v0
1730-
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_3)
17311728
; GFX11-NEXT: v_or_b32_e32 v5, v5, v6
17321729
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
17331730
; GFX11-NEXT: s_clause 0x1

‎llvm/test/CodeGen/AMDGPU/divergence-driven-buildvector.ll

Lines changed: 5 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -450,14 +450,13 @@ define amdgpu_kernel void @uniform_vec_i16_HH(ptr addrspace(1) %out, i32 %a, i32
450450
; GCN: ; %bb.0:
451451
; GCN-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x9
452452
; GCN-NEXT: s_mov_b32 s7, 0xf000
453-
; GCN-NEXT: s_waitcnt lgkmcnt(0)
454-
; GCN-NEXT: s_lshr_b32 s2, s2, 16
455-
; GCN-NEXT: s_and_b32 s3, s3, 0xffff0000
456-
; GCN-NEXT: s_or_b32 s2, s2, s3
457453
; GCN-NEXT: s_mov_b32 s6, -1
454+
; GCN-NEXT: s_waitcnt lgkmcnt(0)
458455
; GCN-NEXT: s_mov_b32 s4, s0
459456
; GCN-NEXT: s_mov_b32 s5, s1
457+
; GCN-NEXT: s_lshr_b32 s0, s3, 16
460458
; GCN-NEXT: v_mov_b32_e32 v0, s2
459+
; GCN-NEXT: v_alignbit_b32 v0, s0, v0, 16
461460
; GCN-NEXT: buffer_store_dword v0, off, s[4:7], 0
462461
; GCN-NEXT: s_endpgm
463462
;
@@ -506,9 +505,8 @@ define i32 @divergent_vec_i16_HH(i32 %a, i32 %b) {
506505
; GCN-LABEL: divergent_vec_i16_HH:
507506
; GCN: ; %bb.0:
508507
; GCN-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
509-
; GCN-NEXT: v_lshrrev_b32_e32 v0, 16, v0
510-
; GCN-NEXT: v_and_b32_e32 v1, 0xffff0000, v1
511-
; GCN-NEXT: v_or_b32_e32 v0, v0, v1
508+
; GCN-NEXT: v_lshrrev_b32_e32 v1, 16, v1
509+
; GCN-NEXT: v_alignbit_b32 v0, v1, v0, 16
512510
; GCN-NEXT: s_setpc_b64 s[30:31]
513511
;
514512
; GFX9-LABEL: divergent_vec_i16_HH:

‎llvm/test/CodeGen/AMDGPU/fneg-modifier-casting.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -182,12 +182,12 @@ define <2 x i16> @fneg_xor_select_v2i16(<2 x i1> %cond, <2 x i16> %arg0, <2 x i1
182182
; GFX7-NEXT: v_cndmask_b32_e32 v0, v4, v2, vcc
183183
; GFX7-NEXT: v_cmp_eq_u32_e32 vcc, 1, v1
184184
; GFX7-NEXT: v_cndmask_b32_e32 v1, v5, v3, vcc
185-
; GFX7-NEXT: v_lshlrev_b32_e32 v1, 16, v1
185+
; GFX7-NEXT: v_xor_b32_e32 v1, 0x8000, v1
186186
; GFX7-NEXT: v_xor_b32_e32 v0, 0x8000, v0
187-
; GFX7-NEXT: v_xor_b32_e32 v1, 0x80000000, v1
187+
; GFX7-NEXT: v_lshlrev_b32_e32 v2, 16, v1
188188
; GFX7-NEXT: v_and_b32_e32 v0, 0xffff, v0
189-
; GFX7-NEXT: v_or_b32_e32 v0, v0, v1
190-
; GFX7-NEXT: v_lshrrev_b32_e32 v1, 16, v1
189+
; GFX7-NEXT: v_or_b32_e32 v0, v0, v2
190+
; GFX7-NEXT: v_and_b32_e32 v1, 0xffff, v1
191191
; GFX7-NEXT: s_setpc_b64 s[30:31]
192192
;
193193
; GFX9-LABEL: fneg_xor_select_v2i16:

‎llvm/test/CodeGen/AMDGPU/fneg.ll

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -238,12 +238,12 @@ define amdgpu_kernel void @s_fneg_v2i16(ptr addrspace(1) %out, i32 %arg) {
238238
}
239239

240240
; FUNC-LABEL: {{^}}v_fneg_v2i16:
241-
; SI: v_lshlrev_b32_e32 v1, 16, v1
241+
; SI: v_xor_b32_e32 v1, 0x8000, v1
242242
; SI: v_xor_b32_e32 v0, 0x8000, v0
243-
; SI: v_xor_b32_e32 v1, 0x80000000, v1
243+
; SI: v_lshlrev_b32_e32 v2, 16, v1
244244
; SI: v_and_b32_e32 v0, 0xffff, v0
245-
; SI: v_or_b32_e32 v0, v0, v1
246-
; SI: v_lshrrev_b32_e32 v1, 16, v1
245+
; SI: v_or_b32_e32 v0, v0, v2
246+
; SI: v_and_b32_e32 v1, 0xffff, v1
247247

248248
; VI: s_waitcnt
249249
; VI-NEXT: v_xor_b32_e32 v0, 0x80008000, v0

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