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LiqinWengLiqinWeng
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[RISCV] Implement RISCVTTIImpl::shouldConsiderAddressTypePromotion for RISCV (llvm#102560)
This optimization helps reduce repeated calculations of base addresses by extracting type extensions when the same base address is accessed multiple times but its offset is a constant.
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4 files changed

+131
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‎llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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@@ -1428,6 +1428,7 @@ RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
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// Disable strict node mutation.
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IsStrictFPEnabled = true;
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EnableExtLdPromotion = true;
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// Let the subtarget decide if a predictable select is more expensive than the
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// corresponding branch. This information is used in CGP/SelectOpt to decide

‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

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@@ -2000,3 +2000,35 @@ bool RISCVTTIImpl::areInlineCompatible(const Function *Caller,
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// target-features.
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return (CallerBits & CalleeBits) == CalleeBits;
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}
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/// See if \p I should be considered for address type promotion. We check if \p
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/// I is a sext with right type and used in memory accesses. If it used in a
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/// "complex" getelementptr, we allow it to be promoted without finding other
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/// sext instructions that sign extended the same initial value. A getelementptr
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/// is considered as "complex" if it has more than 2 operands.
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bool RISCVTTIImpl::shouldConsiderAddressTypePromotion(
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const Instruction &I, bool &AllowPromotionWithoutCommonHeader) {
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bool Considerable = false;
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AllowPromotionWithoutCommonHeader = false;
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if (!isa<SExtInst>(&I))
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return false;
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Type *ConsideredSExtType =
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Type::getInt64Ty(I.getParent()->getParent()->getContext());
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if (I.getType() != ConsideredSExtType)
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return false;
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// See if the sext is the one with the right type and used in at least one
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// GetElementPtrInst.
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for (const User *U : I.users()) {
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if (const GetElementPtrInst *GEPInst = dyn_cast<GetElementPtrInst>(U)) {
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Considerable = true;
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// A getelementptr is considered as "complex" if it has more than 2
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// operands. We will promote a SExt used in such complex GEP as we
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// expect some computation to be merged if they are done on 64 bits.
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if (GEPInst->getNumOperands() > 2) {
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AllowPromotionWithoutCommonHeader = true;
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break;
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}
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}
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}
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return Considerable;
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}

‎llvm/lib/Target/RISCV/RISCVTargetTransformInfo.h

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -397,7 +397,9 @@ class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
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bool shouldFoldTerminatingConditionAfterLSR() const {
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return true;
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}
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bool
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shouldConsiderAddressTypePromotion(const Instruction &I,
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bool &AllowPromotionWithoutCommonHeader);
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std::optional<unsigned> getMinPageSize() const { return 4096; }
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};
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‎llvm/test/CodeGen/RISCV/riscv-codegen-prepare-atp.ll

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@@ -0,0 +1,95 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -passes='require<profile-summary>,function(codegenprepare)' < %s -S | FileCheck %s
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target datalayout = "e-i64:64-f80:128-n8:16:32:64-S128"
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target triple = "riscv64"
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%struct.match_state = type { i64, i64 }
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; %add is also promoted by forking an extra sext.
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define void @promoteTwoOne(i32 %i, i32 %j, ptr %P1, ptr %P2 ) {
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; CHECK-LABEL: define void @promoteTwoOne(
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; CHECK-SAME: i32 [[I:%.*]], i32 [[J:%.*]], ptr [[P1:%.*]], ptr [[P2:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[S2:%.*]] = sext i32 [[I]] to i64
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; CHECK-NEXT: [[PROMOTED2:%.*]] = sext i32 [[J]] to i64
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; CHECK-NEXT: [[S:%.*]] = add nsw i64 [[S2]], [[PROMOTED2]]
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; CHECK-NEXT: [[ADDR1:%.*]] = getelementptr inbounds i64, ptr [[P1]], i64 [[S]]
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; CHECK-NEXT: store i64 [[S]], ptr [[ADDR1]], align 8
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; CHECK-NEXT: [[ADDR2:%.*]] = getelementptr inbounds i64, ptr [[P2]], i64 [[S2]]
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; CHECK-NEXT: store i64 [[S2]], ptr [[ADDR2]], align 8
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; CHECK-NEXT: ret void
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;
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entry:
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%add = add nsw i32 %i, %j
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%s = sext i32 %add to i64
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%addr1 = getelementptr inbounds i64, ptr %P1, i64 %s
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store i64 %s, ptr %addr1
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%s2 = sext i32 %i to i64
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%addr2 = getelementptr inbounds i64, ptr %P2, i64 %s2
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store i64 %s2, ptr %addr2
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ret void
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}
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; Both %add1 and %add2 are promoted by forking extra sexts.
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define void @promoteTwoTwo(i32 %i, i32 %j, i32 %k, ptr %P1, ptr %P2) {
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; CHECK-LABEL: define void @promoteTwoTwo(
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; CHECK-SAME: i32 [[I:%.*]], i32 [[J:%.*]], i32 [[K:%.*]], ptr [[P1:%.*]], ptr [[P2:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[PROMOTED3:%.*]] = sext i32 [[J]] to i64
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; CHECK-NEXT: [[PROMOTED4:%.*]] = sext i32 [[I]] to i64
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; CHECK-NEXT: [[S:%.*]] = add nsw i64 [[PROMOTED3]], [[PROMOTED4]]
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; CHECK-NEXT: [[ADDR1:%.*]] = getelementptr inbounds i64, ptr [[P1]], i64 [[S]]
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; CHECK-NEXT: store i64 [[S]], ptr [[ADDR1]], align 8
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; CHECK-NEXT: [[PROMOTED2:%.*]] = sext i32 [[K]] to i64
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; CHECK-NEXT: [[S2:%.*]] = add nsw i64 [[PROMOTED3]], [[PROMOTED2]]
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; CHECK-NEXT: [[ADDR2:%.*]] = getelementptr inbounds i64, ptr [[P2]], i64 [[S2]]
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; CHECK-NEXT: store i64 [[S2]], ptr [[ADDR2]], align 8
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; CHECK-NEXT: ret void
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;
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entry:
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%add1 = add nsw i32 %j, %i
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%s = sext i32 %add1 to i64
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%addr1 = getelementptr inbounds i64, ptr %P1, i64 %s
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store i64 %s, ptr %addr1
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%add2 = add nsw i32 %j, %k
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%s2 = sext i32 %add2 to i64
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%addr2 = getelementptr inbounds i64, ptr %P2, i64 %s2
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store i64 %s2, ptr %addr2
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ret void
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}
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define i64 @promoteGEPSunk(i1 %cond, ptr %base, i32 %i) {
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; CHECK-LABEL: define i64 @promoteGEPSunk(
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; CHECK-SAME: i1 [[COND:%.*]], ptr [[BASE:%.*]], i32 [[I:%.*]]) {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[PROMOTED1:%.*]] = sext i32 [[I]] to i64
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; CHECK-NEXT: [[S:%.*]] = add nsw i64 [[PROMOTED1]], 1
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; CHECK-NEXT: [[ADDR:%.*]] = getelementptr inbounds i64, ptr [[BASE]], i64 [[S]]
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; CHECK-NEXT: [[S2:%.*]] = add nsw i64 [[PROMOTED1]], 2
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; CHECK-NEXT: [[ADDR2:%.*]] = getelementptr inbounds i64, ptr [[BASE]], i64 [[S2]]
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; CHECK-NEXT: br i1 [[COND]], label [[IF_THEN:%.*]], label [[IF_THEN2:%.*]]
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; CHECK: if.then:
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; CHECK-NEXT: [[V:%.*]] = load i64, ptr [[ADDR]], align 8
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; CHECK-NEXT: [[V2:%.*]] = load i64, ptr [[ADDR2]], align 8
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; CHECK-NEXT: [[R:%.*]] = add i64 [[V]], [[V2]]
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; CHECK-NEXT: ret i64 [[R]]
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; CHECK: if.then2:
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; CHECK-NEXT: ret i64 0
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;
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entry:
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%add = add nsw i32 %i, 1
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%s = sext i32 %add to i64
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%addr = getelementptr inbounds i64, ptr %base, i64 %s
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%add2 = add nsw i32 %i, 2
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%s2 = sext i32 %add2 to i64
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%addr2 = getelementptr inbounds i64, ptr %base, i64 %s2
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br i1 %cond, label %if.then, label %if.then2
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if.then:
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%v = load i64, ptr %addr
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%v2 = load i64, ptr %addr2
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%r = add i64 %v, %v2
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ret i64 %r
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if.then2:
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ret i64 0;
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}

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