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[NFC][ARM] Update tests
Run the update_mir_test on some of the low-overhead loop tests.
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6 files changed

+283
-142
lines changed

6 files changed

+283
-142
lines changed

‎llvm/test/CodeGen/Thumb2/LowOverheadLoops/cond-mov.mir

+34-16
Original file line numberDiff line numberDiff line change
@@ -1,19 +1,17 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
12
# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
2-
# CHECK-NOT: $lr = tMOVr $r0, 13
3-
# CHECK: $lr = t2DLS killed $r0
4-
# CHECK: $lr = t2LEUpdate renamable $lr, %bb.1
53

64
--- |
75
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
86
target triple = "thumbv8.1m.main"
9-
7+
108
define i32 @do_copy(i32 %n, i32* nocapture %p, i32* nocapture readonly %q) {
119
entry:
1210
%scevgep = getelementptr i32, i32* %q, i32 -1
1311
%scevgep3 = getelementptr i32, i32* %p, i32 -1
1412
call void @llvm.set.loop.iterations.i32(i32 %n)
1513
br label %while.body
16-
14+
1715
while.body: ; preds = %while.body, %entry
1816
%lsr.iv4 = phi i32* [ %scevgep5, %while.body ], [ %scevgep3, %entry ]
1917
%lsr.iv = phi i32* [ %scevgep1, %while.body ], [ %scevgep, %entry ]
@@ -27,14 +25,14 @@
2725
%2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
2826
%3 = icmp ne i32 %2, 0
2927
br i1 %3, label %while.body, label %while.end
30-
28+
3129
while.end: ; preds = %while.body
3230
ret i32 0
3331
}
34-
32+
3533
declare void @llvm.set.loop.iterations.i32(i32) #0
3634
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #0
37-
35+
3836
attributes #0 = { noduplicate nounwind }
3937
attributes #1 = { nounwind }
4038

@@ -75,20 +73,40 @@ frameInfo:
7573
restorePoint: ''
7674
fixedStack: []
7775
stack:
78-
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
79-
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
76+
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
77+
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
8078
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
81-
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
82-
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
79+
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
80+
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
8381
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
8482
callSites: []
8583
constants: []
8684
machineFunctionInfo: {}
8785
body: |
86+
; CHECK-LABEL: name: do_copy
87+
; CHECK: bb.0.entry:
88+
; CHECK: successors: %bb.1(0x80000000)
89+
; CHECK: liveins: $r0, $r1, $r2, $r7, $lr
90+
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
91+
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
92+
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
93+
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
94+
; CHECK: $lr = t2DLS killed $r0
95+
; CHECK: renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
96+
; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
97+
; CHECK: bb.1.while.body:
98+
; CHECK: successors: %bb.1(0x7c000000), %bb.2(0x04000000)
99+
; CHECK: liveins: $lr, $r0, $r1
100+
; CHECK: renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6)
101+
; CHECK: early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2)
102+
; CHECK: $lr = t2LEUpdate renamable $lr, %bb.1
103+
; CHECK: bb.2.while.end:
104+
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14, $noreg
105+
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0
88106
bb.0.entry:
89107
successors: %bb.1(0x80000000)
90108
liveins: $r0, $r1, $r2, $r7, $lr
91-
109+
92110
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
93111
frame-setup CFI_INSTRUCTION def_cfa_offset 8
94112
frame-setup CFI_INSTRUCTION offset $lr, -4
@@ -97,17 +115,17 @@ body: |
97115
t2DoLoopStart killed $r0
98116
renamable $r0, dead $cpsr = tSUBi3 killed renamable $r1, 4, 14, $noreg
99117
renamable $r1, dead $cpsr = tSUBi3 killed renamable $r2, 4, 14, $noreg
100-
118+
101119
bb.1.while.body:
102120
successors: %bb.1(0x7c000000), %bb.2(0x04000000)
103121
liveins: $lr, $r0, $r1
104-
122+
105123
renamable $r2, renamable $r1 = t2LDR_PRE killed renamable $r1, 4, 14, $noreg :: (load 4 from %ir.scevgep6)
106124
early-clobber renamable $r0 = t2STR_PRE killed renamable $r2, killed renamable $r0, 4, 14, $noreg :: (store 4 into %ir.scevgep2)
107125
renamable $lr = t2LoopDec killed renamable $lr, 1
108126
t2LoopEnd renamable $lr, %bb.1, implicit-def dead $cpsr
109127
tB %bb.2, 14, $noreg
110-
128+
111129
bb.2.while.end:
112130
$r0, dead $cpsr = tMOVi8 0, 14, $noreg
113131
tPOP_RET 14, $noreg, def $r7, def $pc, implicit killed $r0

‎llvm/test/CodeGen/Thumb2/LowOverheadLoops/end-positive-offset.mir

+86-44
Original file line numberDiff line numberDiff line change
@@ -1,27 +1,18 @@
1+
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
12
# RUN: llc -mtriple=thumbv8.1m.main -run-pass=arm-low-overhead-loops %s -verify-machineinstrs -o - | FileCheck %s
23

3-
# CHECK-NOT: DoLoopStart
4-
# CHECK-NOT: DLS
5-
# CHECK: bb.1.for.body:
6-
# CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr
7-
# CHECK-NOT: t2CMPri $lr
8-
# CHECK: tBcc %bb.3, 1, $cpsr
9-
# CHECK: tB %bb.2, 14, $noreg
10-
# CHECK: bb.2.for.cond.cleanup:
11-
# CHECK: bb.3.for.header:
12-
134
--- |
145
target datalayout = "e-m:e-p:32:32-Fi8-i64:64-v128:64:128-a:0:32-n32-S64"
156
target triple = "thumbv8.1m.main"
16-
7+
178
define void @size_limit(i32* nocapture %a, i32* nocapture readonly %b, i32* nocapture readonly %c, i32 %N) {
189
entry:
1910
call void @llvm.set.loop.iterations.i32(i32 %N)
2011
%scevgep = getelementptr i32, i32* %a, i32 -1
2112
%scevgep4 = getelementptr i32, i32* %c, i32 -1
2213
%scevgep8 = getelementptr i32, i32* %b, i32 -1
2314
br label %for.header
24-
15+
2516
for.body: ; preds = %for.header
2617
%scevgep11 = getelementptr i32, i32* %lsr.iv9, i32 1
2718
%ld1 = load i32, i32* %scevgep11, align 4
@@ -36,27 +27,27 @@
3627
%count.next = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %count, i32 1)
3728
%cmp = icmp ne i32 %count.next, 0
3829
br i1 %cmp, label %for.header, label %for.cond.cleanup
39-
30+
4031
for.cond.cleanup: ; preds = %for.body
4132
ret void
42-
33+
4334
for.header: ; preds = %for.body, %entry
4435
%lsr.iv9 = phi i32* [ %scevgep8, %entry ], [ %scevgep10, %for.body ]
4536
%lsr.iv5 = phi i32* [ %scevgep4, %entry ], [ %scevgep6, %for.body ]
4637
%lsr.iv1 = phi i32* [ %scevgep, %entry ], [ %scevgep2, %for.body ]
4738
%count = phi i32 [ %N, %entry ], [ %count.next, %for.body ]
4839
br label %for.body
4940
}
50-
41+
5142
; Function Attrs: nounwind
5243
declare i32 @llvm.arm.space(i32 immarg, i32) #0
53-
44+
5445
; Function Attrs: noduplicate nounwind
5546
declare void @llvm.set.loop.iterations.i32(i32) #1
56-
47+
5748
; Function Attrs: noduplicate nounwind
5849
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #1
59-
50+
6051
attributes #0 = { nounwind }
6152
attributes #1 = { noduplicate nounwind }
6253

@@ -98,44 +89,95 @@ frameInfo:
9889
restorePoint: ''
9990
fixedStack: []
10091
stack:
101-
- { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
102-
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
92+
- { id: 0, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
93+
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
10394
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
104-
- { id: 1, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
105-
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
95+
- { id: 1, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
96+
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
10697
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
107-
- { id: 2, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
108-
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
98+
- { id: 2, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
99+
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
109100
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
110-
- { id: 3, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
111-
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
101+
- { id: 3, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
102+
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
112103
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
113-
- { id: 4, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
114-
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
104+
- { id: 4, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
105+
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
115106
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
116-
- { id: 5, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
117-
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
107+
- { id: 5, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
108+
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
118109
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
119-
- { id: 6, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4,
120-
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
110+
- { id: 6, name: '', type: spill-slot, offset: -36, size: 4, alignment: 4,
111+
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
121112
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
122-
- { id: 7, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4,
123-
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
113+
- { id: 7, name: '', type: spill-slot, offset: -40, size: 4, alignment: 4,
114+
stack-id: default, callee-saved-register: '', callee-saved-restored: true,
124115
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
125-
- { id: 8, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
126-
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
116+
- { id: 8, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
117+
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: false,
127118
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
128-
- { id: 9, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
129-
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
119+
- { id: 9, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
120+
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
130121
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
131122
callSites: []
132123
constants: []
133124
machineFunctionInfo: {}
134125
body: |
126+
; CHECK-LABEL: name: size_limit
127+
; CHECK: bb.0.entry:
128+
; CHECK: successors: %bb.3(0x80000000)
129+
; CHECK: liveins: $r0, $r1, $r2, $r3, $r7, $lr
130+
; CHECK: frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
131+
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 8
132+
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
133+
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -8
134+
; CHECK: $sp = frame-setup tSUBspi $sp, 8, 14, $noreg
135+
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 40
136+
; CHECK: renamable $r0, dead $cpsr = tSUBi8 killed renamable $r0, 4, 14, $noreg
137+
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
138+
; CHECK: renamable $r1, dead $cpsr = tSUBi8 killed renamable $r1, 4, 14, $noreg
139+
; CHECK: tSTRspi killed $r1, $sp, 7, 14, $noreg :: (store 4 into %stack.0)
140+
; CHECK: tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.1)
141+
; CHECK: tSTRspi killed $r0, $sp, 5, 14, $noreg :: (store 4 into %stack.2)
142+
; CHECK: tSTRspi killed $r3, $sp, 4, 14, $noreg :: (store 4 into %stack.3)
143+
; CHECK: tB %bb.3, 14, $noreg
144+
; CHECK: bb.1.for.body:
145+
; CHECK: successors: %bb.3(0x40000000), %bb.2(0x40000000)
146+
; CHECK: $r0 = tLDRspi $sp, 3, 14, $noreg :: (load 4 from %stack.4)
147+
; CHECK: renamable $r1, renamable $r0 = t2LDR_PRE renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep11)
148+
; CHECK: $r2 = tLDRspi $sp, 2, 14, $noreg :: (load 4 from %stack.5)
149+
; CHECK: renamable $r3, renamable $r2 = t2LDR_PRE renamable $r2, 4, 14, $noreg :: (load 4 from %ir.scevgep7)
150+
; CHECK: renamable $r1, dead $cpsr = nsw tMUL killed renamable $r3, killed renamable $r1, 14, $noreg
151+
; CHECK: $r3 = tLDRspi $sp, 1, 14, $noreg :: (load 4 from %stack.6)
152+
; CHECK: early-clobber renamable $r3 = t2STR_PRE killed renamable $r1, renamable $r3, 4, 14, $noreg :: (store 4 into %ir.scevgep3)
153+
; CHECK: $r1 = tLDRspi $sp, 0, 14, $noreg :: (load 4 from %stack.7)
154+
; CHECK: $lr = tMOVr killed $r1, 14, $noreg
155+
; CHECK: $lr = t2SUBri killed renamable $lr, 1, 14, $noreg, def $cpsr
156+
; CHECK: $r12 = tMOVr $lr, 14, $noreg
157+
; CHECK: tSTRspi killed $r0, $sp, 7, 14, $noreg :: (store 4 into %stack.0)
158+
; CHECK: tSTRspi killed $r2, $sp, 6, 14, $noreg :: (store 4 into %stack.1)
159+
; CHECK: tSTRspi killed $r3, $sp, 5, 14, $noreg :: (store 4 into %stack.2)
160+
; CHECK: t2STRi12 killed $r12, $sp, 16, 14, $noreg :: (store 4 into %stack.3)
161+
; CHECK: tBcc %bb.3, 1, $cpsr
162+
; CHECK: tB %bb.2, 14, $noreg
163+
; CHECK: bb.2.for.cond.cleanup:
164+
; CHECK: $sp = tADDspi $sp, 8, 14, $noreg
165+
; CHECK: tPOP_RET 14, $noreg, def $r7, def $pc
166+
; CHECK: bb.3.for.header:
167+
; CHECK: successors: %bb.1(0x80000000)
168+
; CHECK: $r0 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %stack.3)
169+
; CHECK: $r1 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %stack.2)
170+
; CHECK: $r2 = tLDRspi $sp, 6, 14, $noreg :: (load 4 from %stack.1)
171+
; CHECK: $r3 = tLDRspi $sp, 7, 14, $noreg :: (load 4 from %stack.0)
172+
; CHECK: tSTRspi killed $r0, $sp, 0, 14, $noreg :: (store 4 into %stack.7)
173+
; CHECK: tSTRspi killed $r1, $sp, 1, 14, $noreg :: (store 4 into %stack.6)
174+
; CHECK: tSTRspi killed $r2, $sp, 2, 14, $noreg :: (store 4 into %stack.5)
175+
; CHECK: tSTRspi killed $r3, $sp, 3, 14, $noreg :: (store 4 into %stack.4)
176+
; CHECK: tB %bb.1, 14, $noreg
135177
bb.0.entry:
136178
successors: %bb.3(0x80000000)
137179
liveins: $r0, $r1, $r2, $r3, $r7, $lr
138-
180+
139181
frame-setup tPUSH 14, $noreg, killed $r7, killed $lr, implicit-def $sp, implicit $sp
140182
frame-setup CFI_INSTRUCTION def_cfa_offset 8
141183
frame-setup CFI_INSTRUCTION offset $lr, -4
@@ -151,10 +193,10 @@ body: |
151193
tSTRspi killed $r0, $sp, 5, 14, $noreg :: (store 4 into %stack.2)
152194
tSTRspi killed $r3, $sp, 4, 14, $noreg :: (store 4 into %stack.3)
153195
tB %bb.3, 14, $noreg
154-
196+
155197
bb.1.for.body:
156198
successors: %bb.3(0x40000000), %bb.2(0x40000000)
157-
199+
158200
$r0 = tLDRspi $sp, 3, 14, $noreg :: (load 4 from %stack.4)
159201
renamable $r1, renamable $r0 = t2LDR_PRE renamable $r0, 4, 14, $noreg :: (load 4 from %ir.scevgep11)
160202
$r2 = tLDRspi $sp, 2, 14, $noreg :: (load 4 from %stack.5)
@@ -172,14 +214,14 @@ body: |
172214
t2STRi12 killed $r12, $sp, 16, 14, $noreg :: (store 4 into %stack.3)
173215
t2LoopEnd killed renamable $lr, %bb.3, implicit-def dead $cpsr
174216
tB %bb.2, 14, $noreg
175-
217+
176218
bb.2.for.cond.cleanup:
177219
$sp = tADDspi $sp, 8, 14, $noreg
178220
tPOP_RET 14, $noreg, def $r7, def $pc
179-
221+
180222
bb.3.for.header:
181223
successors: %bb.1(0x80000000)
182-
224+
183225
$r0 = tLDRspi $sp, 4, 14, $noreg :: (load 4 from %stack.3)
184226
$r1 = tLDRspi $sp, 5, 14, $noreg :: (load 4 from %stack.2)
185227
$r2 = tLDRspi $sp, 6, 14, $noreg :: (load 4 from %stack.1)

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