Skip to content

Commit 7a7f223

Browse files
kaz7Simon Moll
kaz7
authored and
Simon Moll
committed
[VE] Update integer arithmetic instructions
Summary: Changing all mnemonic to match assembly instructions to simplify mnemonic naming rules. This time update all fixed-point arithmetic instructions. This also corrects smax/smin code generations. Reviewed By: simoll Differential Revision: https://reviews.llvm.org/D77856
1 parent 3e3701f commit 7a7f223

File tree

4 files changed

+104
-109
lines changed

4 files changed

+104
-109
lines changed

‎llvm/lib/Target/VE/VEFrameLowering.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,7 @@ void VEFrameLowering::emitSPAdjustment(MachineFunction &MF,
121121
*static_cast<const VEInstrInfo *>(MF.getSubtarget().getInstrInfo());
122122

123123
if (NumBytes >= -64 && NumBytes < 63) {
124-
BuildMI(MBB, MBBI, dl, TII.get(VE::ADXri), VE::SX11)
124+
BuildMI(MBB, MBBI, dl, TII.get(VE::ADDSLri), VE::SX11)
125125
.addReg(VE::SX11)
126126
.addImm(NumBytes);
127127
return;

‎llvm/lib/Target/VE/VEInstrInfo.td

Lines changed: 99 additions & 104 deletions
Original file line numberDiff line numberDiff line change
@@ -628,6 +628,10 @@ multiclass CVTm<string opcStr, bits<8> opc,
628628

629629
//===----------------------------------------------------------------------===//
630630
// Instructions
631+
//
632+
// Define all scalar instructions defined in SX-Aurora TSUBASA Architecture
633+
// Guide here. As those mnemonics, we use mnemonics defined in Vector Engine
634+
// Assembly Language Reference Manual.
631635
//===----------------------------------------------------------------------===//
632636

633637
//-----------------------------------------------------------------------------
@@ -773,6 +777,21 @@ defm ST2B : STOREm<"st2b", 0x14, I32, i32, truncstorei16>;
773777
let DecoderMethod = "DecodeStoreI8" in
774778
defm ST1B : STOREm<"st1b", 0x15, I32, i32, truncstorei8>;
775779

780+
// Section 8.2.12 - DLDS
781+
// Section 8.2.13 - DLDU
782+
// Section 8.2.14 - DLDL
783+
// Section 8.2.15 - PFCH
784+
// Section 8.2.16 - TS1AM (Test and Set 1 AM)
785+
// Section 8.2.17 - TS2AM (Test and Set 2 AM)
786+
// Section 8.2.18 - TS3AM (Test and Set 3 AM)
787+
// Section 8.2.19 - ATMAM (Atomic AM)
788+
// Section 8.2.20 - CAS (Compare and Swap)
789+
//-----------------------------------------------------------------------------
790+
// Section 8.3 - Transfer Control Instructions
791+
//-----------------------------------------------------------------------------
792+
// Section 8.3.1 - FENCE (Fence)
793+
// Section 8.3.2 - SVOB (Set Vector Out-of-order memory access Boundary)
794+
776795
// CMOV instructions
777796
let cx = 0, cw = 0, cw2 = 0 in
778797
defm CMOVL : RRCMOVm<"cmov.l.${cf}", 0x3B, I64, i64, simm7, uimm6>;
@@ -786,102 +805,78 @@ defm CMOVD : RRCMOVm<"cmov.d.${cf}", 0x3B, I64, f64, simm7, uimm6>;
786805
let cx = 0, cw = 1, cw2 = 1 in
787806
defm CMOVS : RRCMOVm<"cmov.s.${cf}", 0x3B, F32, f32, simm7, uimm6>;
788807

808+
//-----------------------------------------------------------------------------
809+
// Section 8.4 - Fixed-point Operation Instructions
810+
//-----------------------------------------------------------------------------
789811

790-
// 5.3.2.2. Fixed-Point Arithmetic Operation Instructions
812+
// Section 8.4.1 - ADD (Add)
813+
defm ADDUL : RRm<"addu.l", 0x48, I64, i64>;
814+
let cx = 1 in defm ADDUW : RRm<"addu.w", 0x48, I32, i32>;
791815

792-
// ADD instruction
793-
let cx = 0 in
794-
defm ADD : RRm<"addu.l", 0x48, I64, i64>;
795-
let cx = 1 in
796-
defm ADDUW : RRm<"addu.w", 0x48, I32, i32>;
816+
// Section 8.4.2 - ADS (Add Single)
817+
defm ADDSWSX : RRm<"adds.w.sx", 0x4A, I32, i32, add>;
818+
let cx = 1 in defm ADDSWZX : RRm<"adds.w.zx", 0x4A, I32, i32>;
797819

798-
// ADS instruction
799-
let cx = 0 in
800-
defm ADS : RRm<"adds.w.sx", 0x4A, I32, i32, add>;
801-
let cx = 1 in
802-
defm ADSU : RRm<"adds.w.zx", 0x4A, I32, i32>;
820+
// Section 8.4.3 - ADX (Add)
821+
defm ADDSL : RRm<"adds.l", 0x59, I64, i64, add>;
803822

804-
// ADX instruction
805-
let cx = 0 in
806-
defm ADX : RRm<"adds.l", 0x59, I64, i64, add>;
823+
// Section 8.4.4 - SUB (Subtract)
824+
defm SUBUL : RRNCm<"subu.l", 0x58, I64, i64>;
825+
let cx = 1 in defm SUBUW : RRNCm<"subu.w", 0x58, I32, i32>;
807826

808-
// SUB instruction
809-
let cx = 0 in
810-
defm SUB : RRm<"subu.l", 0x58, I64, i64>;
811-
let cx = 1 in
812-
defm SUBUW : RRm<"subu.w", 0x58, I32, i32>;
827+
// Section 8.4.5 - SBS (Subtract Single)
828+
defm SUBSWSX : RRNCm<"subs.w.sx", 0x5A, I32, i32, sub>;
829+
let cx = 1 in defm SUBSWZX : RRNCm<"subs.w.zx", 0x5A, I32, i32>;
813830

814-
// SBS instruction
815-
let cx = 0 in
816-
defm SBS : RRNCm<"subs.w.sx", 0x5A, I32, i32, sub>;
817-
let cx = 1 in
818-
defm SBSU : RRm<"subs.w.zx", 0x5A, I32, i32>;
831+
// Section 8.4.6 - SBX (Subtract)
832+
defm SUBSL : RRNCm<"subs.l", 0x5B, I64, i64, sub>;
819833

820-
// SBX instruction
821-
let cx = 0 in
822-
defm SBX : RRNCm<"subs.l", 0x5B, I64, i64, sub>;
834+
// Section 8.4.7 - MPY (Multiply)
835+
defm MULUL : RRm<"mulu.l", 0x49, I64, i64>;
836+
let cx = 1 in defm MULUW : RRm<"mulu.w", 0x49, I32, i32>;
823837

824-
// MPY instruction
825-
let cx = 0 in
826-
defm MPY : RRm<"mulu.l", 0x49, I64, i64>;
827-
let cx = 1 in
828-
defm MPYUW : RRm<"mulu.w", 0x49, I32, i32>;
838+
// Section 8.4.8 - MPS (Multiply Single)
839+
defm MULSWSX : RRm<"muls.w.sx", 0x4B, I32, i32, mul>;
840+
let cx = 1 in defm MULSWZX : RRm<"muls.w.zx", 0x4B, I32, i32>;
829841

830-
// MPS instruction
831-
let cx = 0 in
832-
defm MPS : RRm<"muls.w.sx", 0x4B, I32, i32, mul>;
833-
let cx = 1 in
834-
defm MPSU : RRm<"muls.w.zx", 0x4B, I32, i32>;
842+
// Section 8.4.9 - MPX (Multiply)
843+
defm MULSL : RRm<"muls.l", 0x6E, I64, i64, mul>;
835844

836-
// MPX instruction
837-
let cx = 0 in
838-
defm MPX : RRm<"muls.l", 0x6E, I64, i64, mul>;
845+
// Section 8.4.10 - MPD (Multiply)
839846

840-
// DIV instruction
841-
let cx = 0 in
842-
defm DIV : RRNCm<"divu.l", 0x6F, I64, i64, udiv>;
843-
let cx = 1 in
844-
defm DIVUW : RRNCm<"divu.w", 0x6F, I32, i32, udiv>;
847+
// Section 8.4.11 - DIV (Divide)
848+
defm DIVUL : RRNCm<"divu.l", 0x6F, I64, i64, udiv>;
849+
let cx = 1 in defm DIVUW : RRNCm<"divu.w", 0x6F, I32, i32, udiv>;
845850

846-
// DVS instruction
847-
let cx = 0 in
848-
defm DVS : RRNCm<"divs.w.sx", 0x7B, I32, i32, sdiv>;
849-
let cx = 1 in
850-
defm DVSU : RRm<"divs.w.zx", 0x7B, I32, i32>;
851+
// Section 8.4.12 - DVS (Divide Single)
852+
defm DIVSWSX : RRNCm<"divs.w.sx", 0x7B, I32, i32, sdiv>;
853+
let cx = 1 in defm DIVSWZX : RRNCm<"divs.w.zx", 0x7B, I32, i32>;
851854

852-
// DVX instruction
853-
let cx = 0 in
854-
defm DVX : RRNCm<"divs.l", 0x7F, I64, i64, sdiv>;
855+
// Section 8.4.13 - DVX (Divide)
856+
defm DIVSL : RRNCm<"divs.l", 0x7F, I64, i64, sdiv>;
855857

856-
// CMP instruction
857-
let cx = 0 in
858-
defm CMP : RRm<"cmpu.l", 0x55, I64, i64>;
859-
let cx = 1 in
860-
defm CMPUW : RRm<"cmpu.w", 0x55, I32, i32>;
858+
// Section 8.4.14 - CMP (Compare)
859+
defm CMPUL : RRNCm<"cmpu.l", 0x55, I64, i64>;
860+
let cx = 1 in defm CMPUW : RRNCm<"cmpu.w", 0x55, I32, i32>;
861861

862-
// CPS instruction
863-
let cx = 0 in
864-
defm CPS : RRm<"cmps.w.sx", 0x7A, I32, i32>;
865-
let cx = 1 in
866-
defm CPSU : RRm<"cmps.w.zx", 0x7A, I32, i32>;
862+
// Section 8.4.15 - CPS (Compare Single)
863+
defm CMPSWSX : RRNCm<"cmps.w.sx", 0x7A, I32, i32>;
864+
let cx = 1 in defm CMPSWZX : RRNCm<"cmps.w.zx", 0x7A, I32, i32>;
867865

868-
// CPX instruction
869-
let cx = 0 in
870-
defm CPX : RRm<"cmps.l", 0x6A, I64, i64>;
866+
// Section 8.4.16 - CPX (Compare)
867+
defm CMPSL : RRNCm<"cmps.l", 0x6A, I64, i64>;
871868

869+
// Section 8.4.17 - CMS (Compare and Select Maximum/Minimum Single)
872870
// cx: sx/zx, cw: max/min
871+
defm MAXSWSX : RRm<"maxs.w.sx", 0x78, I32, i32>;
872+
let cx = 1 in defm MAXSWZX : RRm<"maxs.w.zx", 0x78, I32, i32>;
873+
let cw = 1 in defm MINSWSX : RRm<"mins.w.sx", 0x78, I32, i32>;
874+
let cx = 1, cw = 1 in defm MINSWZX : RRm<"mins.w.zx", 0x78, I32, i32>;
873875

874-
let cw = 0 in defm CMXa :
875-
RRm<"maxs.l", 0x68, I64, i64>;
876-
877-
let cx = 0, cw = 0 in defm CMSa :
878-
RRm<"maxs.w.zx", 0x78, I32, i32>;
879-
880-
let cw = 1 in defm CMXi :
881-
RRm<"mins.l", 0x68, I64, i64>;
876+
// Section 8.4.18 - CMX (Compare and Select Maximum/Minimum)
877+
defm MAXSL : RRm<"maxs.l", 0x68, I64, i64>;
878+
let cw = 1 in defm MINSL : RRm<"mins.l", 0x68, I64, i64>;
882879

883-
let cx = 1, cw = 0 in defm CMSi :
884-
RRm<"mins.w.zx", 0x78, I32, i32>;
885880

886881
// 5.3.2.3. Logical Arithmetic Operation Instructions
887882

@@ -1148,16 +1143,16 @@ def : Pat<(and (trunc i64:$src), 0xffff),
11481143

11491144
// Cast to i32
11501145
def : Pat<(i32 (trunc i64:$src)),
1151-
(ADSrm (EXTRACT_SUBREG $src, sub_i32), 0)>;
1146+
(ADDSWSXrm (EXTRACT_SUBREG $src, sub_i32), 0)>;
11521147

11531148
// Cast to i64
11541149
def : Pat<(sext_inreg I64:$src, i32),
11551150
(INSERT_SUBREG (i64 (IMPLICIT_DEF)),
1156-
(ADSrm (EXTRACT_SUBREG $src, sub_i32), 0), sub_i32)>;
1151+
(ADDSWSXrm (EXTRACT_SUBREG $src, sub_i32), 0), sub_i32)>;
11571152
def : Pat<(i64 (sext i32:$sy)),
1158-
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (ADSrm $sy, 0), sub_i32)>;
1153+
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (ADDSWSXrm $sy, 0), sub_i32)>;
11591154
def : Pat<(i64 (zext i32:$sy)),
1160-
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (ADSUrm $sy, 0), sub_i32)>;
1155+
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), (ADDSWZXrm $sy, 0), sub_i32)>;
11611156
def : Pat<(i64 (fp_to_sint f32:$sy)), (FIXXr (CVDr $sy))>;
11621157

11631158
// Cast to f32
@@ -1270,7 +1265,7 @@ def : Pat<(brcc CCUIOp:$cond, i32:$l, i32:$r, bb:$addr),
12701265
def : Pat<(brcc CCSIOp:$cond, i64:$l, i64:$r, bb:$addr),
12711266
(BCRLrr (icond2cc $cond), $l, $r, bb:$addr)>;
12721267
def : Pat<(brcc CCUIOp:$cond, i64:$l, i64:$r, bb:$addr),
1273-
(BCRLir (icond2cc $cond), 0, (CMPrr $r, $l), bb:$addr)>;
1268+
(BCRLir (icond2cc $cond), 0, (CMPULrr $r, $l), bb:$addr)>;
12741269
def : Pat<(brcc cond:$cond, f32:$l, f32:$r, bb:$addr),
12751270
(BCRSrr (fcond2cc $cond), $l, $r, bb:$addr)>;
12761271
def : Pat<(brcc cond:$cond, f64:$l, f64:$r, bb:$addr),
@@ -1332,21 +1327,21 @@ def EXTEND_STACK_GUARD : Pseudo<(outs), (ins),
13321327
def : Pat<(i32 (setcc i64:$LHS, i64:$RHS, CCSIOp:$cond)),
13331328
(EXTRACT_SUBREG
13341329
(CMOVLrm0 (icond2cc $cond),
1335-
(CPXrr i64:$LHS, i64:$RHS),
1330+
(CMPSLrr i64:$LHS, i64:$RHS),
13361331
63,
13371332
(ORim 0, 0)), sub_i32)>;
13381333

13391334
def : Pat<(i32 (setcc i64:$LHS, i64:$RHS, CCUIOp:$cond)),
13401335
(EXTRACT_SUBREG
13411336
(CMOVLrm0 (icond2cc $cond),
1342-
(CMPrr i64:$LHS, i64:$RHS),
1337+
(CMPULrr i64:$LHS, i64:$RHS),
13431338
63,
13441339
(ORim 0, 0)), sub_i32)>;
13451340

13461341
def : Pat<(i32 (setcc i32:$LHS, i32:$RHS, CCSIOp:$cond)),
13471342
(EXTRACT_SUBREG
13481343
(CMOVWrm0 (icond2cc $cond),
1349-
(CPSrr i32:$LHS, i32:$RHS),
1344+
(CMPSWSXrr i32:$LHS, i32:$RHS),
13501345
63,
13511346
(ORim 0, 0)), sub_i32)>;
13521347

@@ -1381,34 +1376,34 @@ def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOGT)),
13811376
def : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOGT)),
13821377
(FCMASrr $LHS, $RHS)>;
13831378
def : Pat<(i64 (selectcc i64:$LHS, i64:$RHS, i64:$LHS, i64:$RHS, SETGT)),
1384-
(CMXarr $LHS, $RHS)>;
1379+
(MAXSLrr $LHS, $RHS)>;
13851380
def : Pat<(i32 (selectcc i32:$LHS, i32:$RHS, i32:$LHS, i32:$RHS, SETGT)),
1386-
(CMSarr $LHS, $RHS)>;
1381+
(MAXSWSXrr $LHS, $RHS)>;
13871382
def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOGE)),
13881383
(FCMArr $LHS, $RHS)>;
13891384
def : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOGE)),
13901385
(FCMASrr $LHS, $RHS)>;
13911386
def : Pat<(i64 (selectcc i64:$LHS, i64:$RHS, i64:$LHS, i64:$RHS, SETGE)),
1392-
(CMXarr $LHS, $RHS)>;
1387+
(MAXSLrr $LHS, $RHS)>;
13931388
def : Pat<(i32 (selectcc i32:$LHS, i32:$RHS, i32:$LHS, i32:$RHS, SETGE)),
1394-
(CMSarr $LHS, $RHS)>;
1389+
(MAXSWSXrr $LHS, $RHS)>;
13951390

13961391
def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOLT)),
13971392
(FCMIrr $LHS, $RHS)>;
13981393
def : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOLT)),
13991394
(FCMISrr $LHS, $RHS)>;
14001395
def : Pat<(i64 (selectcc i64:$LHS, i64:$RHS, i64:$LHS, i64:$RHS, SETLT)),
1401-
(CMXirr $LHS, $RHS)>;
1396+
(MINSLrr $LHS, $RHS)>;
14021397
def : Pat<(i32 (selectcc i32:$LHS, i32:$RHS, i32:$LHS, i32:$RHS, SETLT)),
1403-
(CMSirr $LHS, $RHS)>;
1398+
(MINSWSXrr $LHS, $RHS)>;
14041399
def : Pat<(f64 (selectcc f64:$LHS, f64:$RHS, f64:$LHS, f64:$RHS, SETOLE)),
14051400
(FCMIrr $LHS, $RHS)>;
14061401
def : Pat<(f32 (selectcc f32:$LHS, f32:$RHS, f32:$LHS, f32:$RHS, SETOLE)),
14071402
(FCMISrr $LHS, $RHS)>;
14081403
def : Pat<(i64 (selectcc i64:$LHS, i64:$RHS, i64:$LHS, i64:$RHS, SETLE)),
1409-
(CMXirr $LHS, $RHS)>;
1404+
(MINSLrr $LHS, $RHS)>;
14101405
def : Pat<(i32 (selectcc i32:$LHS, i32:$RHS, i32:$LHS, i32:$RHS, SETLE)),
1411-
(CMSirr $LHS, $RHS)>;
1406+
(MINSWSXrr $LHS, $RHS)>;
14121407

14131408
// Generic SELECTCC pattern matches
14141409
//
@@ -1418,13 +1413,13 @@ def : Pat<(i32 (selectcc i32:$LHS, i32:$RHS, i32:$LHS, i32:$RHS, SETLE)),
14181413

14191414
// selectcc for i64 result
14201415
def : Pat<(i64 (selectcc i32:$l, i32:$r, i64:$t, i64:$f, CCSIOp:$cond)),
1421-
(CMOVWrr (icond2cc $cond), (CPSrr $l, $r), $t, $f)>;
1416+
(CMOVWrr (icond2cc $cond), (CMPSWSXrr $l, $r), $t, $f)>;
14221417
def : Pat<(i64 (selectcc i32:$l, i32:$r, i64:$t, i64:$f, CCUIOp:$cond)),
14231418
(CMOVWrr (icond2cc $cond), (CMPUWrr $l, $r), $t, $f)>;
14241419
def : Pat<(i64 (selectcc i64:$l, i64:$r, i64:$t, i64:$f, CCSIOp:$cond)),
1425-
(CMOVLrr (icond2cc $cond), (CPXrr $l, $r), $t, $f)>;
1420+
(CMOVLrr (icond2cc $cond), (CMPSLrr $l, $r), $t, $f)>;
14261421
def : Pat<(i64 (selectcc i64:$l, i64:$r, i64:$t, i64:$f, CCUIOp:$cond)),
1427-
(CMOVLrr (icond2cc $cond), (CMPrr $l, $r), $t, $f)>;
1422+
(CMOVLrr (icond2cc $cond), (CMPULrr $l, $r), $t, $f)>;
14281423
def : Pat<(i64 (selectcc f32:$l, f32:$r, i64:$t, i64:$f, cond:$cond)),
14291424
(CMOVSrr (fcond2cc $cond), (FCPSrr $l, $r), $t, $f)>;
14301425
def : Pat<(i64 (selectcc f64:$l, f64:$r, i64:$t, i64:$f, cond:$cond)),
@@ -1434,7 +1429,7 @@ def : Pat<(i64 (selectcc f64:$l, f64:$r, i64:$t, i64:$f, cond:$cond)),
14341429
def : Pat<(i32 (selectcc i32:$l, i32:$r, i32:$t, i32:$f, CCSIOp:$cond)),
14351430
(EXTRACT_SUBREG
14361431
(CMOVWrr (icond2cc $cond),
1437-
(CPSrr $l, $r),
1432+
(CMPSWSXrr $l, $r),
14381433
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_i32),
14391434
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_i32)),
14401435
sub_i32)>;
@@ -1448,14 +1443,14 @@ def : Pat<(i32 (selectcc i32:$l, i32:$r, i32:$t, i32:$f, CCUIOp:$cond)),
14481443
def : Pat<(i32 (selectcc i64:$l, i64:$r, i32:$t, i32:$f, CCSIOp:$cond)),
14491444
(EXTRACT_SUBREG
14501445
(CMOVLrr (icond2cc $cond),
1451-
(CPXrr $l, $r),
1446+
(CMPSLrr $l, $r),
14521447
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_i32),
14531448
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_i32)),
14541449
sub_i32)>;
14551450
def : Pat<(i32 (selectcc i64:$l, i64:$r, i32:$t, i32:$f, CCUIOp:$cond)),
14561451
(EXTRACT_SUBREG
14571452
(CMOVLrr (icond2cc $cond),
1458-
(CMPrr $l, $r),
1453+
(CMPULrr $l, $r),
14591454
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), $t, sub_i32),
14601455
(INSERT_SUBREG (i64 (IMPLICIT_DEF)), $f, sub_i32)),
14611456
sub_i32)>;
@@ -1476,13 +1471,13 @@ def : Pat<(i32 (selectcc f64:$l, f64:$r, i32:$t, i32:$f, cond:$cond)),
14761471

14771472
// selectcc for f64 result
14781473
def : Pat<(f64 (selectcc i32:$l, i32:$r, f64:$t, f64:$f, CCSIOp:$cond)),
1479-
(CMOVWrr (icond2cc $cond), (CPSrr $l, $r), $t, $f)>;
1474+
(CMOVWrr (icond2cc $cond), (CMPSWSXrr $l, $r), $t, $f)>;
14801475
def : Pat<(f64 (selectcc i32:$l, i32:$r, f64:$t, f64:$f, CCUIOp:$cond)),
14811476
(CMOVWrr (icond2cc $cond), (CMPUWrr $l, $r), $t, $f)>;
14821477
def : Pat<(f64 (selectcc i64:$l, i64:$r, f64:$t, f64:$f, CCSIOp:$cond)),
1483-
(CMOVLrr (icond2cc $cond), (CPXrr $l, $r), $t, $f)>;
1478+
(CMOVLrr (icond2cc $cond), (CMPSLrr $l, $r), $t, $f)>;
14841479
def : Pat<(f64 (selectcc i64:$l, i64:$r, f64:$t, f64:$f, CCUIOp:$cond)),
1485-
(CMOVLrr (icond2cc $cond), (CMPrr $l, $r), $t, $f)>;
1480+
(CMOVLrr (icond2cc $cond), (CMPULrr $l, $r), $t, $f)>;
14861481
def : Pat<(f64 (selectcc f32:$l, f32:$r, f64:$t, f64:$f, cond:$cond)),
14871482
(CMOVSrr (fcond2cc $cond), (FCPSrr $l, $r), $t, $f)>;
14881483
def : Pat<(f64 (selectcc f64:$l, f64:$r, f64:$t, f64:$f, cond:$cond)),
@@ -1492,7 +1487,7 @@ def : Pat<(f64 (selectcc f64:$l, f64:$r, f64:$t, f64:$f, cond:$cond)),
14921487
def : Pat<(f32 (selectcc i32:$l, i32:$r, f32:$t, f32:$f, CCSIOp:$cond)),
14931488
(EXTRACT_SUBREG
14941489
(CMOVWrr (icond2cc $cond),
1495-
(CPSrr $l, $r),
1490+
(CMPSWSXrr $l, $r),
14961491
(INSERT_SUBREG (f64 (IMPLICIT_DEF)), $t, sub_f32),
14971492
(INSERT_SUBREG (f64 (IMPLICIT_DEF)), $f, sub_f32)),
14981493
sub_f32)>;
@@ -1506,14 +1501,14 @@ def : Pat<(f32 (selectcc i32:$l, i32:$r, f32:$t, f32:$f, CCUIOp:$cond)),
15061501
def : Pat<(f32 (selectcc i64:$l, i64:$r, f32:$t, f32:$f, CCSIOp:$cond)),
15071502
(EXTRACT_SUBREG
15081503
(CMOVLrr (icond2cc $cond),
1509-
(CPXrr $l, $r),
1504+
(CMPSLrr $l, $r),
15101505
(INSERT_SUBREG (f64 (IMPLICIT_DEF)), $t, sub_f32),
15111506
(INSERT_SUBREG (f64 (IMPLICIT_DEF)), $f, sub_f32)),
15121507
sub_f32)>;
15131508
def : Pat<(f32 (selectcc i64:$l, i64:$r, f32:$t, f32:$f, CCUIOp:$cond)),
15141509
(EXTRACT_SUBREG
15151510
(CMOVLrr (icond2cc $cond),
1516-
(CMPrr $l, $r),
1511+
(CMPULrr $l, $r),
15171512
(INSERT_SUBREG (f64 (IMPLICIT_DEF)), $t, sub_f32),
15181513
(INSERT_SUBREG (f64 (IMPLICIT_DEF)), $f, sub_f32)),
15191514
sub_f32)>;

‎llvm/test/CodeGen/VE/max.ll

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -141,7 +141,7 @@ define i64 @max2u64(i64, i64) {
141141
define i32 @maxi32(i32, i32) {
142142
; CHECK-LABEL: maxi32:
143143
; CHECK: .LBB{{[0-9]+}}_2:
144-
; CHECK-NEXT: maxs.w.zx %s0, %s0, %s1
144+
; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1
145145
; CHECK-NEXT: or %s11, 0, %s9
146146
%3 = icmp sgt i32 %0, %1
147147
%4 = select i1 %3, i32 %0, i32 %1
@@ -151,7 +151,7 @@ define i32 @maxi32(i32, i32) {
151151
define i32 @max2i32(i32, i32) {
152152
; CHECK-LABEL: max2i32:
153153
; CHECK: .LBB{{[0-9]+}}_2:
154-
; CHECK-NEXT: maxs.w.zx %s0, %s0, %s1
154+
; CHECK-NEXT: maxs.w.sx %s0, %s0, %s1
155155
; CHECK-NEXT: or %s11, 0, %s9
156156
%3 = icmp sge i32 %0, %1
157157
%4 = select i1 %3, i32 %0, i32 %1

0 commit comments

Comments
 (0)