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[LV] Forget LCSSA phi with new pred before other SCEV invalidation. (llvm#119897)
`forgetLcssaPhiWithNewPredecessor` performs additional invalidation if there is an existing SCEV for the phi, but earlier `forgetBlockAndLoopDispositions` or `forgetLoop` may already invalidate the SCEV for the phi. Change the order to first call `forgetLcssaPhiWithNewPredecessor` to ensure it runs before its SCEV gets invalidated too eagerly. Fixes llvm#119665. PR: llvm#119897
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‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -2937,10 +2937,6 @@ void InnerLoopVectorizer::fixVectorizedLoop(VPTransformState &State) {
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if (EnableVPlanNativePath)
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fixNonInductionPHIs(State);
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2940-
// Forget the original basic block.
2941-
PSE.getSE()->forgetLoop(OrigLoop);
2942-
PSE.getSE()->forgetBlockAndLoopDispositions();
2943-
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// After vectorization, the exit blocks of the original loop will have
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// additional predecessors. Invalidate SCEVs for the exit phis in case SE
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// looked through single-entry phis.
@@ -2950,6 +2946,10 @@ void InnerLoopVectorizer::fixVectorizedLoop(VPTransformState &State) {
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for (PHINode &PN : Exit->phis())
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PSE.getSE()->forgetLcssaPhiWithNewPredecessor(OrigLoop, &PN);
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2949+
// Forget the original basic block.
2950+
PSE.getSE()->forgetLoop(OrigLoop);
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PSE.getSE()->forgetBlockAndLoopDispositions();
2952+
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// Don't apply optimizations below when no vector region remains, as they all
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// require a vector loop at the moment.
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if (!State.Plan->getVectorLoopRegion())

‎llvm/test/Transforms/LoopVectorize/invalidate-scev-at-scope-after-vectorization.ll

Lines changed: 118 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,118 @@
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; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 5
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; RUN: opt -passes='print<scalar-evolution>,loop-vectorize' -force-vector-width=4 -scalar-evolution-classify-expressions=false -S %s | FileCheck %s
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; Test case for https://github.com/llvm/llvm-project/issues/119665.
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; %loop.2's backedge-taken-count depends on %add.1 from %loop.1 via its
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; corresponding SCEV at the scope of %loop.2. After vectorizing %loop.1, %add.1
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; isn't available at the entry of %loop.2 anymore and %add.1 at %loop.2's scope
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; must be invalidated, as well as %loop.2's backedge-taken count.
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define void @test_invalidate_scevs_at_scope(ptr %p) {
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; CHECK-LABEL: define void @test_invalidate_scevs_at_scope(
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; CHECK-SAME: ptr [[P:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*]]:
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; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_IND:%.*]] = phi <4 x i32> [ <i32 0, i32 1, i32 2, i32 3>, %[[VECTOR_PH]] ], [ [[VEC_IND_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = load i32, ptr [[P]], align 4
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; CHECK-NEXT: [[BROADCAST_SPLATINSERT:%.*]] = insertelement <4 x i32> poison, i32 [[TMP0]], i64 0
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; CHECK-NEXT: [[BROADCAST_SPLAT:%.*]] = shufflevector <4 x i32> [[BROADCAST_SPLATINSERT]], <4 x i32> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP1:%.*]] = add <4 x i32> [[BROADCAST_SPLAT]], [[VEC_IND]]
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
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; CHECK-NEXT: [[VEC_IND_NEXT]] = add <4 x i32> [[VEC_IND]], splat (i32 4)
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[INDEX_NEXT]], 100
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; CHECK-NEXT: br i1 [[TMP2]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: [[TMP3:%.*]] = extractelement <4 x i32> [[TMP1]], i32 3
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; CHECK-NEXT: br i1 false, label %[[EXIT_1:.*]], label %[[SCALAR_PH]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i32 [ 100, %[[MIDDLE_BLOCK]] ], [ 0, %[[ENTRY]] ]
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; CHECK-NEXT: br label %[[LOOP_1:.*]]
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; CHECK: [[LOOP_1]]:
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; CHECK-NEXT: [[IV_1:%.*]] = phi i32 [ [[BC_RESUME_VAL]], %[[SCALAR_PH]] ], [ [[IV_1_NEXT:%.*]], %[[LOOP_1]] ]
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; CHECK-NEXT: [[TMP4:%.*]] = load i32, ptr [[P]], align 4
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; CHECK-NEXT: [[ADD_1:%.*]] = add i32 [[TMP4]], [[IV_1]]
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; CHECK-NEXT: [[IV_1_NEXT]] = add i32 [[IV_1]], 1
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; CHECK-NEXT: [[C_1:%.*]] = icmp eq i32 [[IV_1]], 100
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; CHECK-NEXT: br i1 [[C_1]], label %[[EXIT_1]], label %[[LOOP_1]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: [[EXIT_1]]:
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; CHECK-NEXT: [[ADD_LCSSA:%.*]] = phi i32 [ [[ADD_1]], %[[LOOP_1]] ], [ [[TMP3]], %[[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: [[SMAX:%.*]] = call i32 @llvm.smax.i32(i32 [[ADD_LCSSA]], i32 100)
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; CHECK-NEXT: [[TMP5:%.*]] = sub i32 [[SMAX]], [[ADD_LCSSA]]
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; CHECK-NEXT: [[TMP6:%.*]] = zext i32 [[TMP5]] to i64
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; CHECK-NEXT: [[TMP7:%.*]] = add nuw nsw i64 [[TMP6]], 1
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; CHECK-NEXT: [[MIN_ITERS_CHECK:%.*]] = icmp ult i64 [[TMP7]], 4
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; CHECK-NEXT: br i1 [[MIN_ITERS_CHECK]], label %[[SCALAR_PH2:.*]], label %[[VECTOR_PH3:.*]]
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; CHECK: [[VECTOR_PH3]]:
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; CHECK-NEXT: [[N_MOD_VF:%.*]] = urem i64 [[TMP7]], 4
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; CHECK-NEXT: [[N_VEC:%.*]] = sub i64 [[TMP7]], [[N_MOD_VF]]
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; CHECK-NEXT: br label %[[VECTOR_BODY4:.*]]
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; CHECK: [[VECTOR_BODY4]]:
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; CHECK-NEXT: [[INDEX5:%.*]] = phi i64 [ 0, %[[VECTOR_PH3]] ], [ [[INDEX_NEXT8:%.*]], %[[VECTOR_BODY4]] ]
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; CHECK-NEXT: [[VEC_IND6:%.*]] = phi <4 x i64> [ <i64 0, i64 1, i64 2, i64 3>, %[[VECTOR_PH3]] ], [ [[VEC_IND_NEXT7:%.*]], %[[VECTOR_BODY4]] ]
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; CHECK-NEXT: [[TMP8:%.*]] = add i64 [[INDEX5]], 0
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr inbounds i64, ptr [[P]], i64 [[TMP8]]
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; CHECK-NEXT: [[TMP10:%.*]] = getelementptr inbounds i64, ptr [[TMP9]], i32 0
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; CHECK-NEXT: store <4 x i64> [[VEC_IND6]], ptr [[TMP10]], align 4
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; CHECK-NEXT: [[INDEX_NEXT8]] = add nuw i64 [[INDEX5]], 4
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; CHECK-NEXT: [[VEC_IND_NEXT7]] = add <4 x i64> [[VEC_IND6]], splat (i64 4)
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; CHECK-NEXT: [[TMP11:%.*]] = icmp eq i64 [[INDEX_NEXT8]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[TMP11]], label %[[MIDDLE_BLOCK1:.*]], label %[[VECTOR_BODY4]], !llvm.loop [[LOOP4:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK1]]:
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 [[TMP7]], [[N_VEC]]
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; CHECK-NEXT: br i1 [[CMP_N]], label %[[EXIT_2:.*]], label %[[SCALAR_PH2]]
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; CHECK: [[SCALAR_PH2]]:
68+
; CHECK-NEXT: [[BC_RESUME_VAL9:%.*]] = phi i64 [ [[N_VEC]], %[[MIDDLE_BLOCK1]] ], [ 0, %[[EXIT_1]] ]
69+
; CHECK-NEXT: br label %[[LOOP_2:.*]]
70+
; CHECK: [[LOOP_2]]:
71+
; CHECK-NEXT: [[IV_2:%.*]] = phi i64 [ [[BC_RESUME_VAL9]], %[[SCALAR_PH2]] ], [ [[IV_2_NEXT:%.*]], %[[LOOP_2]] ]
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; CHECK-NEXT: [[IV_2_TRUNC:%.*]] = trunc i64 [[IV_2]] to i32
73+
; CHECK-NEXT: [[IV_2_NEXT]] = add i64 [[IV_2]], 1
74+
; CHECK-NEXT: [[GEP:%.*]] = getelementptr inbounds i64, ptr [[P]], i64 [[IV_2]]
75+
; CHECK-NEXT: store i64 [[IV_2]], ptr [[GEP]], align 4
76+
; CHECK-NEXT: [[ADD_2:%.*]] = add i32 [[ADD_LCSSA]], [[IV_2_TRUNC]]
77+
; CHECK-NEXT: [[C_2:%.*]] = icmp slt i32 [[ADD_2]], 100
78+
; CHECK-NEXT: br i1 [[C_2]], label %[[LOOP_2]], label %[[EXIT_2]], !llvm.loop [[LOOP5:![0-9]+]]
79+
; CHECK: [[EXIT_2]]:
80+
; CHECK-NEXT: ret void
81+
;
82+
entry:
83+
br label %loop.1
84+
85+
loop.1:
86+
%iv.1 = phi i32 [ 0, %entry ], [ %iv.1.next, %loop.1 ]
87+
%1 = load i32, ptr %p, align 4
88+
%add.1 = add i32 %1, %iv.1
89+
%iv.1.next = add i32 %iv.1, 1
90+
%c.1 = icmp eq i32 %iv.1, 100
91+
br i1 %c.1, label %exit.1, label %loop.1
92+
93+
exit.1:
94+
%add.lcssa = phi i32 [ %add.1, %loop.1 ]
95+
br label %loop.2
96+
97+
loop.2:
98+
%iv.2 = phi i64 [ 0, %exit.1 ], [ %iv.2.next, %loop.2 ]
99+
%iv.2.trunc = trunc i64 %iv.2 to i32
100+
%iv.2.next = add i64 %iv.2, 1
101+
%gep = getelementptr inbounds i64, ptr %p, i64 %iv.2
102+
store i64 %iv.2, ptr %gep
103+
%add.2 = add i32 %add.lcssa, %iv.2.trunc
104+
%c.2 = icmp slt i32 %add.2, 100
105+
br i1 %c.2, label %loop.2, label %exit.2
106+
107+
exit.2:
108+
ret void
109+
}
110+
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;.
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; CHECK: [[LOOP0]] = distinct !{[[LOOP0]], [[META1:![0-9]+]], [[META2:![0-9]+]]}
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; CHECK: [[META1]] = !{!"llvm.loop.isvectorized", i32 1}
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; CHECK: [[META2]] = !{!"llvm.loop.unroll.runtime.disable"}
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; CHECK: [[LOOP3]] = distinct !{[[LOOP3]], [[META2]], [[META1]]}
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; CHECK: [[LOOP4]] = distinct !{[[LOOP4]], [[META1]], [[META2]]}
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; CHECK: [[LOOP5]] = distinct !{[[LOOP5]], [[META2]], [[META1]]}
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;.

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