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Pass shufflevector indices as int instead of unsigned.
No functionality change intended.
1 parent cb1ee34 commit 316b49d

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3 files changed

+57
-59
lines changed

3 files changed

+57
-59
lines changed

‎clang/lib/CodeGen/CGBuiltin.cpp

+1-1
Original file line numberDiff line numberDiff line change
@@ -11747,7 +11747,7 @@ Value *CodeGenFunction::EmitX86BuiltinExpr(unsigned BuiltinID,
1174711747
// Splat the 8-bits of immediate 4 times to help the loop wrap around.
1174811748
Imm = (Imm & 0xff) * 0x01010101;
1174911749

11750-
uint32_t Indices[16];
11750+
int Indices[16];
1175111751
for (unsigned l = 0; l != NumElts; l += NumLaneElts) {
1175211752
for (unsigned i = 0; i != NumLaneElts; ++i) {
1175311753
unsigned Index = Imm % NumLaneElts;

‎llvm/lib/IR/AutoUpgrade.cpp

+24-26
Original file line numberDiff line numberDiff line change
@@ -912,7 +912,7 @@ static Value *UpgradeX86PSLLDQIntrinsics(IRBuilder<> &Builder,
912912
// If shift is less than 16, emit a shuffle to move the bytes. Otherwise,
913913
// we'll just return the zero vector.
914914
if (Shift < 16) {
915-
uint32_t Idxs[64];
915+
int Idxs[64];
916916
// 256/512-bit version is split into 2/4 16-byte lanes.
917917
for (unsigned l = 0; l != NumElts; l += 16)
918918
for (unsigned i = 0; i != 16; ++i) {
@@ -946,7 +946,7 @@ static Value *UpgradeX86PSRLDQIntrinsics(IRBuilder<> &Builder, Value *Op,
946946
// If shift is less than 16, emit a shuffle to move the bytes. Otherwise,
947947
// we'll just return the zero vector.
948948
if (Shift < 16) {
949-
uint32_t Idxs[64];
949+
int Idxs[64];
950950
// 256/512-bit version is split into 2/4 16-byte lanes.
951951
for (unsigned l = 0; l != NumElts; l += 16)
952952
for (unsigned i = 0; i != 16; ++i) {
@@ -972,7 +972,7 @@ static Value *getX86MaskVec(IRBuilder<> &Builder, Value *Mask,
972972
// If we have less than 8 elements, then the starting mask was an i8 and
973973
// we need to extract down to the right number of elements.
974974
if (NumElts < 8) {
975-
uint32_t Indices[4];
975+
int Indices[4];
976976
for (unsigned i = 0; i != NumElts; ++i)
977977
Indices[i] = i;
978978
Mask = Builder.CreateShuffleVector(Mask, Mask,
@@ -1041,7 +1041,7 @@ static Value *UpgradeX86ALIGNIntrinsics(IRBuilder<> &Builder, Value *Op0,
10411041
Op0 = llvm::Constant::getNullValue(Op0->getType());
10421042
}
10431043

1044-
uint32_t Indices[64];
1044+
int Indices[64];
10451045
// 256-bit palignr operates on 128-bit lanes so we need to handle that
10461046
for (unsigned l = 0; l < NumElts; l += 16) {
10471047
for (unsigned i = 0; i != 16; ++i) {
@@ -1352,7 +1352,7 @@ static Value *ApplyX86MaskOn1BitsVec(IRBuilder<> &Builder, Value *Vec,
13521352
}
13531353

13541354
if (NumElts < 8) {
1355-
uint32_t Indices[8];
1355+
int Indices[8];
13561356
for (unsigned i = 0; i != NumElts; ++i)
13571357
Indices[i] = i;
13581358
for (unsigned i = NumElts; i != 8; ++i)
@@ -1878,7 +1878,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
18781878
unsigned NumElts = CI->getType()->getScalarSizeInBits();
18791879
Value *LHS = getX86MaskVec(Builder, CI->getArgOperand(0), NumElts);
18801880
Value *RHS = getX86MaskVec(Builder, CI->getArgOperand(1), NumElts);
1881-
uint32_t Indices[64];
1881+
int Indices[64];
18821882
for (unsigned i = 0; i != NumElts; ++i)
18831883
Indices[i] = i;
18841884

@@ -2127,8 +2127,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
21272127
unsigned NumDstElts = DstTy->getNumElements();
21282128
if (NumDstElts < SrcTy->getNumElements()) {
21292129
assert(NumDstElts == 2 && "Unexpected vector size");
2130-
uint32_t ShuffleMask[2] = { 0, 1 };
2131-
Rep = Builder.CreateShuffleVector(Rep, Rep, ShuffleMask);
2130+
Rep = Builder.CreateShuffleVector(Rep, Rep, ArrayRef<int>{0, 1});
21322131
}
21332132

21342133
bool IsPS2PD = SrcTy->getElementType()->isFloatTy();
@@ -2159,8 +2158,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
21592158
unsigned NumDstElts = DstTy->getNumElements();
21602159
if (NumDstElts != SrcTy->getNumElements()) {
21612160
assert(NumDstElts == 4 && "Unexpected vector size");
2162-
uint32_t ShuffleMask[4] = {0, 1, 2, 3};
2163-
Rep = Builder.CreateShuffleVector(Rep, Rep, ShuffleMask);
2161+
Rep = Builder.CreateShuffleVector(Rep, Rep, ArrayRef<int>{0, 1, 2, 3});
21642162
}
21652163
Rep = Builder.CreateBitCast(
21662164
Rep, VectorType::get(Type::getHalfTy(C), NumDstElts));
@@ -2310,7 +2308,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
23102308
unsigned NumDstElts = DstTy->getNumElements();
23112309

23122310
// Extract a subvector of the first NumDstElts lanes and sign/zero extend.
2313-
SmallVector<uint32_t, 8> ShuffleMask(NumDstElts);
2311+
SmallVector<int, 8> ShuffleMask(NumDstElts);
23142312
for (unsigned i = 0; i != NumDstElts; ++i)
23152313
ShuffleMask[i] = i;
23162314

@@ -2356,7 +2354,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
23562354
unsigned NumElementsInLane = 128 / VT->getScalarSizeInBits();
23572355
unsigned ControlBitsMask = NumLanes - 1;
23582356
unsigned NumControlBits = NumLanes / 2;
2359-
SmallVector<uint32_t, 8> ShuffleMask(0);
2357+
SmallVector<int, 8> ShuffleMask(0);
23602358

23612359
for (unsigned l = 0; l != NumLanes; ++l) {
23622360
unsigned LaneMask = (Imm >> (l * NumControlBits)) & ControlBitsMask;
@@ -2376,7 +2374,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
23762374
cast<VectorType>(CI->getArgOperand(0)->getType())->getNumElements();
23772375
unsigned NumDstElts = cast<VectorType>(CI->getType())->getNumElements();
23782376

2379-
SmallVector<uint32_t, 8> ShuffleMask(NumDstElts);
2377+
SmallVector<int, 8> ShuffleMask(NumDstElts);
23802378
for (unsigned i = 0; i != NumDstElts; ++i)
23812379
ShuffleMask[i] = i % NumSrcElts;
23822380

@@ -2466,7 +2464,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
24662464
VectorType *VecTy = cast<VectorType>(CI->getType());
24672465
unsigned NumElts = VecTy->getNumElements();
24682466

2469-
SmallVector<uint32_t, 16> Idxs(NumElts);
2467+
SmallVector<int, 16> Idxs(NumElts);
24702468
for (unsigned i = 0; i != NumElts; ++i)
24712469
Idxs[i] = ((Imm >> (i%8)) & 1) ? i + NumElts : i;
24722470

@@ -2486,7 +2484,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
24862484

24872485
// Extend the second operand into a vector the size of the destination.
24882486
Value *UndefV = UndefValue::get(Op1->getType());
2489-
SmallVector<uint32_t, 8> Idxs(DstNumElts);
2487+
SmallVector<int, 8> Idxs(DstNumElts);
24902488
for (unsigned i = 0; i != SrcNumElts; ++i)
24912489
Idxs[i] = i;
24922490
for (unsigned i = SrcNumElts; i != DstNumElts; ++i)
@@ -2529,7 +2527,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
25292527
Imm = Imm % Scale;
25302528

25312529
// Get indexes for the subvector of the input vector.
2532-
SmallVector<uint32_t, 8> Idxs(DstNumElts);
2530+
SmallVector<int, 8> Idxs(DstNumElts);
25332531
for (unsigned i = 0; i != DstNumElts; ++i) {
25342532
Idxs[i] = i + (Imm * DstNumElts);
25352533
}
@@ -2548,7 +2546,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
25482546
VectorType *VecTy = cast<VectorType>(CI->getType());
25492547
unsigned NumElts = VecTy->getNumElements();
25502548

2551-
SmallVector<uint32_t, 8> Idxs(NumElts);
2549+
SmallVector<int, 8> Idxs(NumElts);
25522550
for (unsigned i = 0; i != NumElts; ++i)
25532551
Idxs[i] = (i & ~0x3) + ((Imm >> (2 * (i & 0x3))) & 3);
25542552

@@ -2571,7 +2569,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
25712569

25722570
unsigned NumElts = cast<VectorType>(CI->getType())->getNumElements();
25732571
unsigned HalfSize = NumElts / 2;
2574-
SmallVector<uint32_t, 8> ShuffleMask(NumElts);
2572+
SmallVector<int, 8> ShuffleMask(NumElts);
25752573

25762574
// Determine which operand(s) are actually in use for this instruction.
25772575
Value *V0 = (Imm & 0x02) ? CI->getArgOperand(1) : CI->getArgOperand(0);
@@ -2605,7 +2603,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
26052603
unsigned IdxSize = 64 / VecTy->getScalarSizeInBits();
26062604
unsigned IdxMask = ((1 << IdxSize) - 1);
26072605

2608-
SmallVector<uint32_t, 8> Idxs(NumElts);
2606+
SmallVector<int, 8> Idxs(NumElts);
26092607
// Lookup the bits for this element, wrapping around the immediate every
26102608
// 8-bits. Elements are grouped into sets of 2 or 4 elements so we need
26112609
// to offset by the first index of each group.
@@ -2623,7 +2621,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
26232621
unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
26242622
unsigned NumElts = cast<VectorType>(CI->getType())->getNumElements();
26252623

2626-
SmallVector<uint32_t, 16> Idxs(NumElts);
2624+
SmallVector<int, 16> Idxs(NumElts);
26272625
for (unsigned l = 0; l != NumElts; l += 8) {
26282626
for (unsigned i = 0; i != 4; ++i)
26292627
Idxs[i + l] = ((Imm >> (2 * i)) & 0x3) + l;
@@ -2642,7 +2640,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
26422640
unsigned Imm = cast<ConstantInt>(CI->getArgOperand(1))->getZExtValue();
26432641
unsigned NumElts = cast<VectorType>(CI->getType())->getNumElements();
26442642

2645-
SmallVector<uint32_t, 16> Idxs(NumElts);
2643+
SmallVector<int, 16> Idxs(NumElts);
26462644
for (unsigned l = 0; l != NumElts; l += 8) {
26472645
for (unsigned i = 0; i != 4; ++i)
26482646
Idxs[i + l] = i + l;
@@ -2664,7 +2662,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
26642662
unsigned NumLaneElts = 128/CI->getType()->getScalarSizeInBits();
26652663
unsigned HalfLaneElts = NumLaneElts / 2;
26662664

2667-
SmallVector<uint32_t, 16> Idxs(NumElts);
2665+
SmallVector<int, 16> Idxs(NumElts);
26682666
for (unsigned i = 0; i != NumElts; ++i) {
26692667
// Base index is the starting element of the lane.
26702668
Idxs[i] = i - (i % NumLaneElts);
@@ -2691,7 +2689,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
26912689
if (Name.startswith("avx512.mask.movshdup."))
26922690
Offset = 1;
26932691

2694-
SmallVector<uint32_t, 16> Idxs(NumElts);
2692+
SmallVector<int, 16> Idxs(NumElts);
26952693
for (unsigned l = 0; l != NumElts; l += NumLaneElts)
26962694
for (unsigned i = 0; i != NumLaneElts; i += 2) {
26972695
Idxs[i + l + 0] = i + l + Offset;
@@ -2709,7 +2707,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
27092707
int NumElts = cast<VectorType>(CI->getType())->getNumElements();
27102708
int NumLaneElts = 128/CI->getType()->getScalarSizeInBits();
27112709

2712-
SmallVector<uint32_t, 64> Idxs(NumElts);
2710+
SmallVector<int, 64> Idxs(NumElts);
27132711
for (int l = 0; l != NumElts; l += NumLaneElts)
27142712
for (int i = 0; i != NumLaneElts; ++i)
27152713
Idxs[i + l] = l + (i / 2) + NumElts * (i % 2);
@@ -2725,7 +2723,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
27252723
int NumElts = cast<VectorType>(CI->getType())->getNumElements();
27262724
int NumLaneElts = 128/CI->getType()->getScalarSizeInBits();
27272725

2728-
SmallVector<uint32_t, 64> Idxs(NumElts);
2726+
SmallVector<int, 64> Idxs(NumElts);
27292727
for (int l = 0; l != NumElts; l += NumLaneElts)
27302728
for (int i = 0; i != NumLaneElts; ++i)
27312729
Idxs[i + l] = (NumLaneElts / 2) + l + (i / 2) + NumElts * (i % 2);
@@ -3304,7 +3302,7 @@ void llvm::UpgradeIntrinsicCall(CallInst *CI, Function *NewFn) {
33043302
if (IsSubAdd)
33053303
std::swap(Even, Odd);
33063304

3307-
SmallVector<uint32_t, 32> Idxs(NumElts);
3305+
SmallVector<int, 32> Idxs(NumElts);
33083306
for (int i = 0; i != NumElts; ++i)
33093307
Idxs[i] = i + (i % 2) * NumElts;
33103308

‎llvm/lib/Target/X86/X86InterleavedAccess.cpp

+32-32
Original file line numberDiff line numberDiff line change
@@ -229,11 +229,11 @@ static MVT scaleVectorType(MVT VT) {
229229
VT.getVectorNumElements() / 2);
230230
}
231231

232-
static uint32_t Concat[] = {
233-
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
234-
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
235-
32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
236-
48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63 };
232+
static constexpr int Concat[] = {
233+
0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15,
234+
16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31,
235+
32, 33, 34, 35, 36, 37, 38, 39, 40, 41, 42, 43, 44, 45, 46, 47,
236+
48, 49, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63};
237237

238238
// genShuffleBland - Creates shuffle according to two vectors.This function is
239239
// only works on instructions with lane inside 256 registers. According to
@@ -251,9 +251,9 @@ static uint32_t Concat[] = {
251251
// By computing the shuffle on a sequence of 16 elements(one lane) and add the
252252
// correct offset. We are creating a vpsuffed + blend sequence between two
253253
// shuffles.
254-
static void genShuffleBland(MVT VT, ArrayRef<uint32_t> Mask,
255-
SmallVectorImpl<uint32_t> &Out, int LowOffset,
256-
int HighOffset) {
254+
static void genShuffleBland(MVT VT, ArrayRef<int> Mask,
255+
SmallVectorImpl<int> &Out, int LowOffset,
256+
int HighOffset) {
257257
assert(VT.getSizeInBits() >= 256 &&
258258
"This function doesn't accept width smaller then 256");
259259
unsigned NumOfElm = VT.getVectorNumElements();
@@ -282,9 +282,9 @@ static void genShuffleBland(MVT VT, ArrayRef<uint32_t> Mask,
282282
// Invec[2] - |2|5|8|11| TransposedMatrix[2] - |8|9|10|11|
283283

284284
static void reorderSubVector(MVT VT, SmallVectorImpl<Value *> &TransposedMatrix,
285-
ArrayRef<Value *> Vec, ArrayRef<uint32_t> VPShuf,
286-
unsigned VecElems, unsigned Stride,
287-
IRBuilder<> &Builder) {
285+
ArrayRef<Value *> Vec, ArrayRef<int> VPShuf,
286+
unsigned VecElems, unsigned Stride,
287+
IRBuilder<> &Builder) {
288288

289289
if (VecElems == 16) {
290290
for (unsigned i = 0; i < Stride; i++)
@@ -293,7 +293,7 @@ static void reorderSubVector(MVT VT, SmallVectorImpl<Value *> &TransposedMatrix,
293293
return;
294294
}
295295

296-
SmallVector<uint32_t, 32> OptimizeShuf;
296+
SmallVector<int, 32> OptimizeShuf;
297297
Value *Temp[8];
298298

299299
for (unsigned i = 0; i < (VecElems / 16) * Stride; i += 2) {
@@ -433,7 +433,7 @@ void X86InterleavedAccessGroup::interleave8bitStride4(
433433
// For example shuffle pattern for VF 16 register size 256 -> lanes = 2
434434
// {<[0|3|6|1|4|7|2|5]-[8|11|14|9|12|15|10|13]>}
435435
static void createShuffleStride(MVT VT, int Stride,
436-
SmallVectorImpl<uint32_t> &Mask) {
436+
SmallVectorImpl<int> &Mask) {
437437
int VectorSize = VT.getSizeInBits();
438438
int VF = VT.getVectorNumElements();
439439
int LaneCount = std::max(VectorSize / 128, 1);
@@ -446,7 +446,7 @@ static void createShuffleStride(MVT VT, int Stride,
446446
// inside mask a shuffleMask. A mask contains exactly 3 groups, where
447447
// each group is a monotonically increasing sequence with stride 3.
448448
// For example shuffleMask {0,3,6,1,4,7,2,5} => {3,3,2}
449-
static void setGroupSize(MVT VT, SmallVectorImpl<uint32_t> &SizeInfo) {
449+
static void setGroupSize(MVT VT, SmallVectorImpl<int> &SizeInfo) {
450450
int VectorSize = VT.getSizeInBits();
451451
int VF = VT.getVectorNumElements() / std::max(VectorSize / 128, 1);
452452
for (int i = 0, FirstGroupElement = 0; i < 3; i++) {
@@ -470,7 +470,7 @@ static void setGroupSize(MVT VT, SmallVectorImpl<uint32_t> &SizeInfo) {
470470
// direction of the alignment. (false - align to the "right" side while true -
471471
// align to the "left" side)
472472
static void DecodePALIGNRMask(MVT VT, unsigned Imm,
473-
SmallVectorImpl<uint32_t> &ShuffleMask,
473+
SmallVectorImpl<int> &ShuffleMask,
474474
bool AlignDirection = true, bool Unary = false) {
475475
unsigned NumElts = VT.getVectorNumElements();
476476
unsigned NumLanes = std::max((int)VT.getSizeInBits() / 128, 1);
@@ -547,11 +547,11 @@ void X86InterleavedAccessGroup::deinterleave8bitStride3(
547547
// Matrix[2]= b5 c5 a6 b6 c6 a7 b7 c7
548548

549549
TransposedMatrix.resize(3);
550-
SmallVector<uint32_t, 32> VPShuf;
551-
SmallVector<uint32_t, 32> VPAlign[2];
552-
SmallVector<uint32_t, 32> VPAlign2;
553-
SmallVector<uint32_t, 32> VPAlign3;
554-
SmallVector<uint32_t, 3> GroupSize;
550+
SmallVector<int, 32> VPShuf;
551+
SmallVector<int, 32> VPAlign[2];
552+
SmallVector<int, 32> VPAlign2;
553+
SmallVector<int, 32> VPAlign3;
554+
SmallVector<int, 3> GroupSize;
555555
Value *Vec[6], *TempVector[3];
556556

557557
MVT VT = MVT::getVT(Shuffles[0]->getType());
@@ -605,8 +605,8 @@ void X86InterleavedAccessGroup::deinterleave8bitStride3(
605605
// group2Shuffle reorder the shuffle stride back into continuous order.
606606
// For example For VF16 with Mask1 = {0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13} =>
607607
// MaskResult = {0,11,6,1,12,7,2,13,8,3,14,9,4,15,10,5}.
608-
static void group2Shuffle(MVT VT, SmallVectorImpl<uint32_t> &Mask,
609-
SmallVectorImpl<uint32_t> &Output) {
608+
static void group2Shuffle(MVT VT, SmallVectorImpl<int> &Mask,
609+
SmallVectorImpl<int> &Output) {
610610
int IndexGroup[3] = {0, 0, 0};
611611
int Index = 0;
612612
int VectorWidth = VT.getSizeInBits();
@@ -633,11 +633,11 @@ void X86InterleavedAccessGroup::interleave8bitStride3(
633633
// Matrix[2]= c0 c1 c2 c3 c3 a7 b7 c7
634634

635635
TransposedMatrix.resize(3);
636-
SmallVector<uint32_t, 3> GroupSize;
637-
SmallVector<uint32_t, 32> VPShuf;
638-
SmallVector<uint32_t, 32> VPAlign[3];
639-
SmallVector<uint32_t, 32> VPAlign2;
640-
SmallVector<uint32_t, 32> VPAlign3;
636+
SmallVector<int, 3> GroupSize;
637+
SmallVector<int, 32> VPShuf;
638+
SmallVector<int, 32> VPAlign[3];
639+
SmallVector<int, 32> VPAlign2;
640+
SmallVector<int, 32> VPAlign3;
641641

642642
Value *Vec[3], *TempVector[3];
643643
MVT VT = MVT::getVectorVT(MVT::i8, VecElems);
@@ -692,25 +692,25 @@ void X86InterleavedAccessGroup::transpose_4x4(
692692
TransposedMatrix.resize(4);
693693

694694
// dst = src1[0,1],src2[0,1]
695-
uint32_t IntMask1[] = {0, 1, 4, 5};
696-
ArrayRef<uint32_t> Mask = makeArrayRef(IntMask1, 4);
695+
static constexpr int IntMask1[] = {0, 1, 4, 5};
696+
ArrayRef<int> Mask = makeArrayRef(IntMask1, 4);
697697
Value *IntrVec1 = Builder.CreateShuffleVector(Matrix[0], Matrix[2], Mask);
698698
Value *IntrVec2 = Builder.CreateShuffleVector(Matrix[1], Matrix[3], Mask);
699699

700700
// dst = src1[2,3],src2[2,3]
701-
uint32_t IntMask2[] = {2, 3, 6, 7};
701+
static constexpr int IntMask2[] = {2, 3, 6, 7};
702702
Mask = makeArrayRef(IntMask2, 4);
703703
Value *IntrVec3 = Builder.CreateShuffleVector(Matrix[0], Matrix[2], Mask);
704704
Value *IntrVec4 = Builder.CreateShuffleVector(Matrix[1], Matrix[3], Mask);
705705

706706
// dst = src1[0],src2[0],src1[2],src2[2]
707-
uint32_t IntMask3[] = {0, 4, 2, 6};
707+
static constexpr int IntMask3[] = {0, 4, 2, 6};
708708
Mask = makeArrayRef(IntMask3, 4);
709709
TransposedMatrix[0] = Builder.CreateShuffleVector(IntrVec1, IntrVec2, Mask);
710710
TransposedMatrix[2] = Builder.CreateShuffleVector(IntrVec3, IntrVec4, Mask);
711711

712712
// dst = src1[1],src2[1],src1[3],src2[3]
713-
uint32_t IntMask4[] = {1, 5, 3, 7};
713+
static constexpr int IntMask4[] = {1, 5, 3, 7};
714714
Mask = makeArrayRef(IntMask4, 4);
715715
TransposedMatrix[1] = Builder.CreateShuffleVector(IntrVec1, IntrVec2, Mask);
716716
TransposedMatrix[3] = Builder.CreateShuffleVector(IntrVec3, IntrVec4, Mask);

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