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[PowerPC] Add support for -mcpu=pwr11 / -mtune=pwr11 (llvm#99511)
This PR adds support for -mcpu=pwr11/power11 and -mtune=pwr11/power11 in clang and llvm.
1 parent 1ebfc81 commit 1df4d86

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15 files changed

+120
-27
lines changed

15 files changed

+120
-27
lines changed

‎clang/lib/Basic/Targets/PPC.cpp

Lines changed: 26 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -385,6 +385,8 @@ void PPCTargetInfo::getTargetDefines(const LangOptions &Opts,
385385
Builder.defineMacro("_ARCH_PWR9");
386386
if (ArchDefs & ArchDefinePwr10)
387387
Builder.defineMacro("_ARCH_PWR10");
388+
if (ArchDefs & ArchDefinePwr11)
389+
Builder.defineMacro("_ARCH_PWR11");
388390
if (ArchDefs & ArchDefineA2)
389391
Builder.defineMacro("_ARCH_A2");
390392
if (ArchDefs & ArchDefineE500)
@@ -622,10 +624,17 @@ bool PPCTargetInfo::initFeatureMap(
622624
addP10SpecificFeatures(Features);
623625
}
624626

625-
// Future CPU should include all of the features of Power 10 as well as any
627+
// Power11 includes all the same features as Power10 plus any features
628+
// specific to the Power11 core.
629+
if (CPU == "pwr11" || CPU == "power11") {
630+
initFeatureMap(Features, Diags, "pwr10", FeaturesVec);
631+
addP11SpecificFeatures(Features);
632+
}
633+
634+
// Future CPU should include all of the features of Power 11 as well as any
626635
// additional features (yet to be determined) specific to it.
627636
if (CPU == "future") {
628-
initFeatureMap(Features, Diags, "pwr10", FeaturesVec);
637+
initFeatureMap(Features, Diags, "pwr11", FeaturesVec);
629638
addFutureSpecificFeatures(Features);
630639
}
631640

@@ -696,6 +705,10 @@ void PPCTargetInfo::addP10SpecificFeatures(
696705
Features["isa-v31-instructions"] = true;
697706
}
698707

708+
// Add any Power11 specific features.
709+
void PPCTargetInfo::addP11SpecificFeatures(
710+
llvm::StringMap<bool> &Features) const {}
711+
699712
// Add features specific to the "Future" CPU.
700713
void PPCTargetInfo::addFutureSpecificFeatures(
701714
llvm::StringMap<bool> &Features) const {}
@@ -870,17 +883,17 @@ ArrayRef<TargetInfo::AddlRegName> PPCTargetInfo::getGCCAddlRegNames() const {
870883
}
871884

872885
static constexpr llvm::StringLiteral ValidCPUNames[] = {
873-
{"generic"}, {"440"}, {"450"}, {"601"}, {"602"},
874-
{"603"}, {"603e"}, {"603ev"}, {"604"}, {"604e"},
875-
{"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"},
876-
{"7450"}, {"g4+"}, {"750"}, {"8548"}, {"970"},
877-
{"g5"}, {"a2"}, {"e500"}, {"e500mc"}, {"e5500"},
878-
{"power3"}, {"pwr3"}, {"power4"}, {"pwr4"}, {"power5"},
879-
{"pwr5"}, {"power5x"}, {"pwr5x"}, {"power6"}, {"pwr6"},
880-
{"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"}, {"power8"},
881-
{"pwr8"}, {"power9"}, {"pwr9"}, {"power10"}, {"pwr10"},
882-
{"powerpc"}, {"ppc"}, {"ppc32"}, {"powerpc64"}, {"ppc64"},
883-
{"powerpc64le"}, {"ppc64le"}, {"future"}};
886+
{"generic"}, {"440"}, {"450"}, {"601"}, {"602"},
887+
{"603"}, {"603e"}, {"603ev"}, {"604"}, {"604e"},
888+
{"620"}, {"630"}, {"g3"}, {"7400"}, {"g4"},
889+
{"7450"}, {"g4+"}, {"750"}, {"8548"}, {"970"},
890+
{"g5"}, {"a2"}, {"e500"}, {"e500mc"}, {"e5500"},
891+
{"power3"}, {"pwr3"}, {"power4"}, {"pwr4"}, {"power5"},
892+
{"pwr5"}, {"power5x"}, {"pwr5x"}, {"power6"}, {"pwr6"},
893+
{"power6x"}, {"pwr6x"}, {"power7"}, {"pwr7"}, {"power8"},
894+
{"pwr8"}, {"power9"}, {"pwr9"}, {"power10"}, {"pwr10"},
895+
{"power11"}, {"pwr11"}, {"powerpc"}, {"ppc"}, {"ppc32"},
896+
{"powerpc64"}, {"ppc64"}, {"powerpc64le"}, {"ppc64le"}, {"future"}};
884897

885898
bool PPCTargetInfo::isValidCPUName(StringRef Name) const {
886899
return llvm::is_contained(ValidCPUNames, Name);

‎clang/lib/Basic/Targets/PPC.h

Lines changed: 13 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -44,8 +44,9 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
4444
ArchDefinePwr8 = 1 << 12,
4545
ArchDefinePwr9 = 1 << 13,
4646
ArchDefinePwr10 = 1 << 14,
47-
ArchDefineFuture = 1 << 15,
48-
ArchDefineA2 = 1 << 16,
47+
ArchDefinePwr11 = 1 << 15,
48+
ArchDefineFuture = 1 << 16,
49+
ArchDefineA2 = 1 << 17,
4950
ArchDefineE500 = 1 << 18
5051
} ArchDefineTypes;
5152

@@ -166,11 +167,16 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
166167
ArchDefinePwr7 | ArchDefinePwr6 | ArchDefinePwr5x |
167168
ArchDefinePwr5 | ArchDefinePwr4 | ArchDefinePpcgr |
168169
ArchDefinePpcsq)
170+
.Cases("power11", "pwr11",
171+
ArchDefinePwr11 | ArchDefinePwr10 | ArchDefinePwr9 |
172+
ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
173+
ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
174+
ArchDefinePpcgr | ArchDefinePpcsq)
169175
.Case("future",
170-
ArchDefineFuture | ArchDefinePwr10 | ArchDefinePwr9 |
171-
ArchDefinePwr8 | ArchDefinePwr7 | ArchDefinePwr6 |
172-
ArchDefinePwr5x | ArchDefinePwr5 | ArchDefinePwr4 |
173-
ArchDefinePpcgr | ArchDefinePpcsq)
176+
ArchDefineFuture | ArchDefinePwr11 | ArchDefinePwr10 |
177+
ArchDefinePwr9 | ArchDefinePwr8 | ArchDefinePwr7 |
178+
ArchDefinePwr6 | ArchDefinePwr5x | ArchDefinePwr5 |
179+
ArchDefinePwr4 | ArchDefinePpcgr | ArchDefinePpcsq)
174180
.Cases("8548", "e500", ArchDefineE500)
175181
.Default(ArchDefineNone);
176182
}
@@ -192,6 +198,7 @@ class LLVM_LIBRARY_VISIBILITY PPCTargetInfo : public TargetInfo {
192198
const std::vector<std::string> &FeaturesVec) const override;
193199

194200
void addP10SpecificFeatures(llvm::StringMap<bool> &Features) const;
201+
void addP11SpecificFeatures(llvm::StringMap<bool> &Features) const;
195202
void addFutureSpecificFeatures(llvm::StringMap<bool> &Features) const;
196203

197204
bool handleTargetFeatures(std::vector<std::string> &Features,

‎clang/lib/Driver/ToolChains/Arch/PPC.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -70,6 +70,7 @@ static std::string normalizeCPUName(StringRef CPUName, const llvm::Triple &T) {
7070
.Case("power8", "pwr8")
7171
.Case("power9", "pwr9")
7272
.Case("power10", "pwr10")
73+
.Case("power11", "pwr11")
7374
.Case("future", "future")
7475
.Case("powerpc", "ppc")
7576
.Case("powerpc64", "ppc64")
@@ -103,6 +104,8 @@ const char *ppc::getPPCAsmModeForCPU(StringRef Name) {
103104
.Case("power9", "-mpower9")
104105
.Case("pwr10", "-mpower10")
105106
.Case("power10", "-mpower10")
107+
.Case("pwr11", "-mpower11")
108+
.Case("power11", "-mpower11")
106109
.Default("-many");
107110
}
108111

‎clang/test/Misc/target-invalid-cpu-note.c

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -57,7 +57,7 @@
5757

5858
// RUN: not %clang_cc1 -triple powerpc--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix PPC
5959
// PPC: error: unknown target CPU 'not-a-cpu'
60-
// PPC-NEXT: note: valid target CPU values are: generic, 440, 450, 601, 602, 603, 603e, 603ev, 604, 604e, 620, 630, g3, 7400, g4, 7450, g4+, 750, 8548, 970, g5, a2, e500, e500mc, e5500, power3, pwr3, power4, pwr4, power5, pwr5, power5x, pwr5x, power6, pwr6, power6x, pwr6x, power7, pwr7, power8, pwr8, power9, pwr9, power10, pwr10, powerpc, ppc, ppc32, powerpc64, ppc64, powerpc64le, ppc64le, future{{$}}
60+
// PPC-NEXT: note: valid target CPU values are: generic, 440, 450, 601, 602, 603, 603e, 603ev, 604, 604e, 620, 630, g3, 7400, g4, 7450, g4+, 750, 8548, 970, g5, a2, e500, e500mc, e5500, power3, pwr3, power4, pwr4, power5, pwr5, power5x, pwr5x, power6, pwr6, power6x, pwr6x, power7, pwr7, power8, pwr8, power9, pwr9, power10, pwr10, power11, pwr11, powerpc, ppc, ppc32, powerpc64, ppc64, powerpc64le, ppc64le, future{{$}}
6161

6262
// RUN: not %clang_cc1 -triple mips--- -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix MIPS
6363
// MIPS: error: unknown target CPU 'not-a-cpu'

‎clang/test/Preprocessor/init-ppc64.c

Lines changed: 22 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -632,13 +632,35 @@
632632
// PPCPOWER10:#define __PCREL__ 1
633633
// PPCPOWER10-NOT:#define __ROP_PROTECT__ 1
634634
//
635+
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu pwr11 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER11 %s
636+
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu power11 -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCPOWER11 %s
637+
//
638+
// PPCPOWER11:#define _ARCH_PPC 1
639+
// PPCPOWER11:#define _ARCH_PPC64 1
640+
// PPCPOWER11:#define _ARCH_PPCGR 1
641+
// PPCPOWER11:#define _ARCH_PPCSQ 1
642+
// PPCPOWER11:#define _ARCH_PWR10 1
643+
// PPCPOWER11:#define _ARCH_PWR11 1
644+
// PPCPOWER11:#define _ARCH_PWR4 1
645+
// PPCPOWER11:#define _ARCH_PWR5 1
646+
// PPCPOWER11:#define _ARCH_PWR5X 1
647+
// PPCPOWER11:#define _ARCH_PWR6 1
648+
// PPCPOWER11-NOT:#define _ARCH_PWR6X 1
649+
// PPCPOWER11:#define _ARCH_PWR7 1
650+
// PPCPOWER11:#define _ARCH_PWR8 1
651+
// PPCPOWER11:#define _ARCH_PWR9 1
652+
// PPCPOWER11:#define __MMA__ 1
653+
// PPCPOWER11:#define __PCREL__ 1
654+
// PPCPOWER11-NOT:#define __ROP_PROTECT__ 1
655+
//
635656
// RUN: %clang_cc1 -E -dM -ffreestanding -triple=powerpc64-none-none -target-cpu future -fno-signed-char < /dev/null | FileCheck -match-full-lines -check-prefix PPCFUTURE %s
636657
//
637658
// PPCFUTURE:#define _ARCH_PPC 1
638659
// PPCFUTURE:#define _ARCH_PPC64 1
639660
// PPCFUTURE:#define _ARCH_PPCGR 1
640661
// PPCFUTURE:#define _ARCH_PPCSQ 1
641662
// PPCFUTURE:#define _ARCH_PWR10 1
663+
// PPCFUTURE:#define _ARCH_PWR11 1
642664
// PPCFUTURE:#define _ARCH_PWR4 1
643665
// PPCFUTURE:#define _ARCH_PWR5 1
644666
// PPCFUTURE:#define _ARCH_PWR5X 1

‎llvm/lib/Target/PowerPC/PPC.td

Lines changed: 17 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -52,6 +52,7 @@ def DirectivePwr7: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR7", "">;
5252
def DirectivePwr8: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR8", "">;
5353
def DirectivePwr9: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR9", "">;
5454
def DirectivePwr10: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR10", "">;
55+
def DirectivePwr11: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR11", "">;
5556
def DirectivePwrFuture
5657
: SubtargetFeature<"", "CPUDirective", "PPC::DIR_PWR_FUTURE", "">;
5758

@@ -467,13 +468,25 @@ def ProcessorFeatures {
467468
list<SubtargetFeature> P10Features =
468469
!listconcat(P10InheritableFeatures, P10SpecificFeatures);
469470

470-
// Future
471-
// For future CPU we assume that all of the existing features from Power10
471+
// Power11
472+
// For P11 CPU we assume that all the existing features from Power10
472473
// still exist with the exception of those we know are Power10 specific.
474+
list<SubtargetFeature> P11AdditionalFeatures =
475+
[DirectivePwr11];
476+
list<SubtargetFeature> P11SpecificFeatures =
477+
[];
478+
list<SubtargetFeature> P11InheritableFeatures =
479+
!listconcat(P10InheritableFeatures, P11AdditionalFeatures);
480+
list<SubtargetFeature> P11Features =
481+
!listconcat(P11InheritableFeatures, P11SpecificFeatures);
482+
483+
// Future
484+
// For future CPU we assume that all of the existing features from Power11
485+
// still exist with the exception of those we know are Power11 specific.
473486
list<SubtargetFeature> FutureAdditionalFeatures = [FeatureISAFuture];
474487
list<SubtargetFeature> FutureSpecificFeatures = [];
475488
list<SubtargetFeature> FutureInheritableFeatures =
476-
!listconcat(P10InheritableFeatures, FutureAdditionalFeatures);
489+
!listconcat(P11InheritableFeatures, FutureAdditionalFeatures);
477490
list<SubtargetFeature> FutureFeatures =
478491
!listconcat(FutureInheritableFeatures, FutureSpecificFeatures);
479492
}
@@ -672,6 +685,7 @@ def : ProcessorModel<"pwr7", P7Model, ProcessorFeatures.P7Features>;
672685
def : ProcessorModel<"pwr8", P8Model, ProcessorFeatures.P8Features>;
673686
def : ProcessorModel<"pwr9", P9Model, ProcessorFeatures.P9Features>;
674687
def : ProcessorModel<"pwr10", P10Model, ProcessorFeatures.P10Features>;
688+
def : ProcessorModel<"pwr11", P10Model, ProcessorFeatures.P11Features>;
675689
// No scheduler model for future CPU.
676690
def : ProcessorModel<"future", NoSchedModel,
677691
ProcessorFeatures.FutureFeatures>;

‎llvm/lib/Target/PowerPC/PPCISelLowering.cpp

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1469,6 +1469,7 @@ PPCTargetLowering::PPCTargetLowering(const PPCTargetMachine &TM,
14691469
case PPC::DIR_PWR8:
14701470
case PPC::DIR_PWR9:
14711471
case PPC::DIR_PWR10:
1472+
case PPC::DIR_PWR11:
14721473
case PPC::DIR_PWR_FUTURE:
14731474
setPrefLoopAlignment(Align(16));
14741475
setPrefFunctionAlignment(Align(16));
@@ -16664,6 +16665,7 @@ Align PPCTargetLowering::getPrefLoopAlignment(MachineLoop *ML) const {
1666416665
case PPC::DIR_PWR8:
1666516666
case PPC::DIR_PWR9:
1666616667
case PPC::DIR_PWR10:
16668+
case PPC::DIR_PWR11:
1666716669
case PPC::DIR_PWR_FUTURE: {
1666816670
if (!ML)
1666916671
break;
@@ -18046,6 +18048,7 @@ SDValue PPCTargetLowering::combineMUL(SDNode *N, DAGCombinerInfo &DCI) const {
1804618048
return true;
1804718049
case PPC::DIR_PWR9:
1804818050
case PPC::DIR_PWR10:
18051+
case PPC::DIR_PWR11:
1804918052
case PPC::DIR_PWR_FUTURE:
1805018053
// type mul add shl
1805118054
// scalar 5 2 2

‎llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -3485,6 +3485,7 @@ unsigned PPCInstrInfo::getSpillTarget() const {
34853485
// With P10, we may need to spill paired vector registers or accumulator
34863486
// registers. MMA implies paired vectors, so we can just check that.
34873487
bool IsP10Variant = Subtarget.isISA3_1() || Subtarget.pairedVectorMemops();
3488+
// P11 uses the P10 target.
34883489
return Subtarget.isISAFuture() ? 3 : IsP10Variant ?
34893490
2 : Subtarget.hasP9Vector() ?
34903491
1 : 0;

‎llvm/lib/Target/PowerPC/PPCSubtarget.h

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,7 @@ enum {
6161
DIR_PWR8,
6262
DIR_PWR9,
6363
DIR_PWR10,
64+
DIR_PWR11,
6465
DIR_PWR_FUTURE,
6566
DIR_64
6667
};

‎llvm/lib/Target/PowerPC/PPCTargetTransformInfo.cpp

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -504,7 +504,7 @@ unsigned PPCTTIImpl::getCacheLineSize() const {
504504
// Assume that Future CPU has the same cache line size as the others.
505505
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
506506
Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
507-
Directive == PPC::DIR_PWR_FUTURE)
507+
Directive == PPC::DIR_PWR11 || Directive == PPC::DIR_PWR_FUTURE)
508508
return 128;
509509

510510
// On other processors return a default of 64 bytes.
@@ -538,7 +538,7 @@ unsigned PPCTTIImpl::getMaxInterleaveFactor(ElementCount VF) {
538538
// Assume that future is the same as the others.
539539
if (Directive == PPC::DIR_PWR7 || Directive == PPC::DIR_PWR8 ||
540540
Directive == PPC::DIR_PWR9 || Directive == PPC::DIR_PWR10 ||
541-
Directive == PPC::DIR_PWR_FUTURE)
541+
Directive == PPC::DIR_PWR11 || Directive == PPC::DIR_PWR_FUTURE)
542542
return 12;
543543

544544
// For most things, modern systems have two execution units (and

‎llvm/lib/TargetParser/Host.cpp

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -150,6 +150,7 @@ StringRef sys::detail::getHostCPUNameForPowerPC(StringRef ProcCpuinfoContent) {
150150
.Case("POWER8NVL", "pwr8")
151151
.Case("POWER9", "pwr9")
152152
.Case("POWER10", "pwr10")
153+
.Case("POWER11", "pwr11")
153154
// FIXME: If we get a simulator or machine with the capabilities of
154155
// mcpu=future, we should revisit this and add the name reported by the
155156
// simulator/machine.
@@ -1549,6 +1550,12 @@ StringRef sys::getHostCPUName() {
15491550
case 0x40000:
15501551
#endif
15511552
return "pwr10";
1553+
#ifdef POWER_11
1554+
case POWER_11:
1555+
#else
1556+
case 0x80000:
1557+
#endif
1558+
return "pwr11";
15521559
default:
15531560
return "generic";
15541561
}

‎llvm/test/CodeGen/PowerPC/check-cpu.ll

Lines changed: 5 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3,6 +3,10 @@
33
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
44
; RUN: -mcpu=future < %s 2>&1 | FileCheck %s
55
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
6+
; RUN: -mcpu=pwr11 < %s 2>&1 | FileCheck %s
7+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
8+
; RUN: -mcpu=pwr11 < %s 2>&1 | FileCheck %s
9+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
610
; RUN: -mcpu=pwr10 < %s 2>&1 | FileCheck %s
711
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
812
; RUN: -mcpu=pwr10 < %s 2>&1 | FileCheck %s
@@ -13,7 +17,7 @@
1317

1418

1519

16-
; Test -mcpu=[pwr9|pwr10|future] is recognized on PowerPC.
20+
; Test -mcpu=[pwr9|pwr10|pwr11|future] is recognized on PowerPC.
1721

1822
; CHECK-NOT: is not a recognized processor for this target
1923
; CHECK: .text

‎llvm/test/CodeGen/PowerPC/mma-acc-spill.ll

Lines changed: 7 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -6,6 +6,13 @@
66
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -disable-auto-paired-vec-st=false \
77
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
88

9+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
10+
; RUN: -mcpu=pwr11 -ppc-asm-full-reg-names -disable-auto-paired-vec-st=false \
11+
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s
12+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
13+
; RUN: -mcpu=pwr11 -ppc-asm-full-reg-names -disable-auto-paired-vec-st=false \
14+
; RUN: -ppc-vsr-nums-as-vr < %s | FileCheck %s --check-prefix=CHECK-BE
15+
916
declare <512 x i1> @llvm.ppc.mma.xvf16ger2pp(<512 x i1>, <16 x i8>, <16 x i8>)
1017
declare <512 x i1> @llvm.ppc.mma.assemble.acc(<16 x i8>, <16 x i8>, <16 x i8>, <16 x i8>)
1118
declare void @foo()

‎llvm/test/CodeGen/PowerPC/p10-constants.ll renamed to ‎llvm/test/CodeGen/PowerPC/p10-p11-constants.ll

Lines changed: 11 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -8,7 +8,17 @@
88
; RUN: -mcpu=pwr10 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
99
; RUN: FileCheck %s --check-prefix=CHECK32
1010

11-
; These test cases aim to test constant materialization using the pli instruction on Power10.
11+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64le-unknown-linux-gnu \
12+
; RUN: -mcpu=pwr11 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
13+
; RUN: FileCheck %s
14+
; RUN: llc -verify-machineinstrs -mtriple=powerpc64-unknown-linux-gnu \
15+
; RUN: -mcpu=pwr11 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
16+
; RUN: FileCheck %s
17+
; RUN: llc -verify-machineinstrs -mtriple=powerpc-unknown-linux-gnu \
18+
; RUN: -mcpu=pwr11 -ppc-asm-full-reg-names -ppc-vsr-nums-as-vr < %s | \
19+
; RUN: FileCheck %s --check-prefix=CHECK32
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; These test cases aim to test constant materialization using the pli instruction on Power10 and Power11.
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define signext i32 @t_16BitsMinRequiring34Bits() {
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; CHECK-LABEL: t_16BitsMinRequiring34Bits:

‎llvm/unittests/TargetParser/Host.cpp

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Original file line numberDiff line numberDiff line change
@@ -536,6 +536,7 @@ TEST(HostTest, AIXHostCPUDetect) {
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.Case("POWER 8\n", "pwr8")
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.Case("POWER 9\n", "pwr9")
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.Case("POWER 10\n", "pwr10")
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.Case("POWER 11\n", "pwr11")
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.Default("unknown");
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StringRef HostCPU = sys::getHostCPUName();

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