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[SveEmitter] Add builtins for various FP operations
Unary: - svexpa, svtmad, svtsmul, svtssel, svscale, svrecpe, svrecps, svrsqrte, svrsqrts, Binary: - svabd, svadd, svdiv, svdivr, svmin, svmax, svminnm, svmaxnm, svmul, svmulx, svsub, svsubr, svmul_lane Complex: - svcadd, svcmla
1 parent 8fac07a commit 1a720d4

36 files changed

+3864
-3
lines changed

‎clang/include/clang/Basic/arm_sve.td

Lines changed: 49 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -74,6 +74,7 @@
7474
// w: vector of element type promoted to 64bits, vector maintains
7575
// signedness of its element type.
7676
// j: element type promoted to 64bits (splat to vector type)
77+
// K: element type bitcast to a signed integer (splat to vector type)
7778
// i: constant uint64_t
7879
// k: int32_t
7980
// l: int64_t
@@ -786,7 +787,41 @@ defm SVREVW : SInstZPZ<"svrevw", "lUl", "aarch64_sve_revw">;
786787
defm SVABS_F : SInstZPZ<"svabs", "hfd", "aarch64_sve_fabs">;
787788
defm SVNEG_F : SInstZPZ<"svneg", "hfd", "aarch64_sve_fneg">;
788789

790+
defm SVABD_F : SInstZPZZ<"svabd", "hfd", "aarch64_sve_fabd">;
791+
defm SVADD_F : SInstZPZZ<"svadd", "hfd", "aarch64_sve_fadd">;
792+
defm SVDIV_F : SInstZPZZ<"svdiv", "hfd", "aarch64_sve_fdiv">;
793+
defm SVDIVR_F : SInstZPZZ<"svdivr", "hfd", "aarch64_sve_fdivr">;
794+
defm SVMAX_F : SInstZPZZ<"svmax", "hfd", "aarch64_sve_fmax">;
795+
defm SVMAXNM : SInstZPZZ<"svmaxnm","hfd", "aarch64_sve_fmaxnm">;
796+
defm SVMIN_F : SInstZPZZ<"svmin", "hfd", "aarch64_sve_fmin">;
797+
defm SVMINNM : SInstZPZZ<"svminnm","hfd", "aarch64_sve_fminnm">;
798+
defm SVMUL_F : SInstZPZZ<"svmul", "hfd", "aarch64_sve_fmul">;
799+
defm SVMULX : SInstZPZZ<"svmulx", "hfd", "aarch64_sve_fmulx">;
800+
defm SVSUB_F : SInstZPZZ<"svsub", "hfd", "aarch64_sve_fsub">;
801+
defm SVSUBR_F : SInstZPZZ<"svsubr", "hfd", "aarch64_sve_fsubr">;
802+
803+
defm SVRECPX : SInstZPZ<"svrecpx", "hfd", "aarch64_sve_frecpx">;
804+
defm SVRINTA : SInstZPZ<"svrinta", "hfd", "aarch64_sve_frinta">;
805+
defm SVRINTI : SInstZPZ<"svrinti", "hfd", "aarch64_sve_frinti">;
806+
defm SVRINTM : SInstZPZ<"svrintm", "hfd", "aarch64_sve_frintm">;
807+
defm SVRINTN : SInstZPZ<"svrintn", "hfd", "aarch64_sve_frintn">;
808+
defm SVRINTP : SInstZPZ<"svrintp", "hfd", "aarch64_sve_frintp">;
809+
defm SVRINTX : SInstZPZ<"svrintx", "hfd", "aarch64_sve_frintx">;
810+
defm SVRINTZ : SInstZPZ<"svrintz", "hfd", "aarch64_sve_frintz">;
811+
defm SVSQRT : SInstZPZ<"svsqrt", "hfd", "aarch64_sve_fsqrt">;
812+
813+
def SVEXPA : SInst<"svexpa[_{d}]", "du", "hfd", MergeNone, "aarch64_sve_fexpa_x">;
789814
def SVTMAD : SInst<"svtmad[_{d}]", "dddi", "hfd", MergeNone, "aarch64_sve_ftmad_x", [], [ImmCheck<2, ImmCheck0_7>]>;
815+
def SVTSMUL : SInst<"svtsmul[_{d}]", "ddu", "hfd", MergeNone, "aarch64_sve_ftsmul_x">;
816+
def SVTSSEL : SInst<"svtssel[_{d}]", "ddu", "hfd", MergeNone, "aarch64_sve_ftssel_x">;
817+
818+
def SVSCALE_M : SInst<"svscale[_{d}]", "dPdx", "hfd", MergeOp1, "aarch64_sve_fscale">;
819+
def SVSCALE_X : SInst<"svscale[_{d}]", "dPdx", "hfd", MergeAny, "aarch64_sve_fscale">;
820+
def SVSCALE_Z : SInst<"svscale[_{d}]", "dPdx", "hfd", MergeZero, "aarch64_sve_fscale">;
821+
822+
def SVSCALE_N_M : SInst<"svscale[_n_{d}]", "dPdK", "hfd", MergeOp1, "aarch64_sve_fscale">;
823+
def SVSCALE_N_X : SInst<"svscale[_n_{d}]", "dPdK", "hfd", MergeAny, "aarch64_sve_fscale">;
824+
def SVSCALE_N_Z : SInst<"svscale[_n_{d}]", "dPdK", "hfd", MergeZero, "aarch64_sve_fscale">;
790825

791826
defm SVMAD_F : SInstZPZZZ<"svmad", "hfd", "aarch64_sve_fmad">;
792827
defm SVMLA_F : SInstZPZZZ<"svmla", "hfd", "aarch64_sve_fmla">;
@@ -797,10 +832,24 @@ defm SVNMLA_F : SInstZPZZZ<"svnmla", "hfd", "aarch64_sve_fnmla">;
797832
defm SVNMLS_F : SInstZPZZZ<"svnmls", "hfd", "aarch64_sve_fnmls">;
798833
defm SVNMSB_F : SInstZPZZZ<"svnmsb", "hfd", "aarch64_sve_fnmsb">;
799834

835+
def SVCADD_M : SInst<"svcadd[_{d}]", "dPddi", "hfd", MergeOp1, "aarch64_sve_fcadd", [], [ImmCheck<3, ImmCheckComplexRot90_270>]>;
836+
def SVCADD_X : SInst<"svcadd[_{d}]", "dPddi", "hfd", MergeAny, "aarch64_sve_fcadd", [], [ImmCheck<3, ImmCheckComplexRot90_270>]>;
837+
def SVCADD_Z : SInst<"svcadd[_{d}]", "dPddi", "hfd", MergeZero, "aarch64_sve_fcadd", [], [ImmCheck<3, ImmCheckComplexRot90_270>]>;
838+
def SVCMLA_M : SInst<"svcmla[_{d}]", "dPdddi", "hfd", MergeOp1, "aarch64_sve_fcmla", [], [ImmCheck<4, ImmCheckComplexRotAll90>]>;
839+
def SVCMLA_X : SInst<"svcmla[_{d}]", "dPdddi", "hfd", MergeAny, "aarch64_sve_fcmla", [], [ImmCheck<4, ImmCheckComplexRotAll90>]>;
840+
def SVCMLA_Z : SInst<"svcmla[_{d}]", "dPdddi", "hfd", MergeZero, "aarch64_sve_fcmla", [], [ImmCheck<4, ImmCheckComplexRotAll90>]>;
841+
800842
def SVCMLA_LANE : SInst<"svcmla_lane[_{d}]", "ddddii", "hf", MergeNone, "aarch64_sve_fcmla_lane", [], [ImmCheck<3, ImmCheckLaneIndexCompRotate, 2>,
801843
ImmCheck<4, ImmCheckComplexRotAll90>]>;
802844
def SVMLA_LANE : SInst<"svmla_lane[_{d}]", "ddddi", "hfd", MergeNone, "aarch64_sve_fmla_lane", [], [ImmCheck<3, ImmCheckLaneIndex, 2>]>;
803845
def SVMLS_LANE : SInst<"svmls_lane[_{d}]", "ddddi", "hfd", MergeNone, "aarch64_sve_fmls_lane", [], [ImmCheck<3, ImmCheckLaneIndex, 2>]>;
846+
def SVMUL_LANE : SInst<"svmul_lane[_{d}]", "dddi", "hfd", MergeNone, "aarch64_sve_fmul_lane", [], [ImmCheck<2, ImmCheckLaneIndex, 1>]>;
847+
848+
def SVRECPE : SInst<"svrecpe[_{d}]", "dd", "hfd", MergeNone, "aarch64_sve_frecpe_x">;
849+
def SVRECPS : SInst<"svrecps[_{d}]", "ddd", "hfd", MergeNone, "aarch64_sve_frecps_x">;
850+
def SVRSQRTE : SInst<"svrsqrte[_{d}]", "dd", "hfd", MergeNone, "aarch64_sve_frsqrte_x">;
851+
def SVRSQRTS : SInst<"svrsqrts[_{d}]", "ddd", "hfd", MergeNone, "aarch64_sve_frsqrts_x">;
852+
804853

805854
////////////////////////////////////////////////////////////////////////////////
806855
// Floating-point comparisons
@@ -928,9 +977,6 @@ def SVCVTXNT_F32 : SInst<"svcvtxnt_f32[_f64]", "MMPd", "d", MergeOp1, "aarch6
928977

929978
}
930979

931-
def SVCADD_M : SInst<"svcadd[_{d}]", "dPddi", "hfd", MergeOp1, "aarch64_sve_fcadd", [], [ImmCheck<3, ImmCheckComplexRot90_270>]>;
932-
def SVCMLA_M : SInst<"svcmla[_{d}]", "dPdddi", "hfd", MergeOp1, "aarch64_sve_fcmla", [], [ImmCheck<4, ImmCheckComplexRotAll90>]>;
933-
934980
////////////////////////////////////////////////////////////////////////////////
935981
// Permutations and selection
936982

‎clang/test/CodeGen/aarch64-sve-intrinsics/acle_sve_abd.c

Lines changed: 177 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -469,3 +469,180 @@ svuint64_t test_svabd_n_u64_x(svbool_t pg, svuint64_t op1, uint64_t op2)
469469
// CHECK: ret <vscale x 2 x i64> %[[INTRINSIC]]
470470
return SVE_ACLE_FUNC(svabd,_n_u64,_x,)(pg, op1, op2);
471471
}
472+
473+
svfloat16_t test_svabd_f16_z(svbool_t pg, svfloat16_t op1, svfloat16_t op2)
474+
{
475+
// CHECK-LABEL: test_svabd_f16_z
476+
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
477+
// CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> zeroinitializer)
478+
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fabd.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %[[SEL]], <vscale x 8 x half> %op2)
479+
// CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
480+
return SVE_ACLE_FUNC(svabd,_f16,_z,)(pg, op1, op2);
481+
}
482+
483+
svfloat32_t test_svabd_f32_z(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
484+
{
485+
// CHECK-LABEL: test_svabd_f32_z
486+
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
487+
// CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.sel.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> zeroinitializer)
488+
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fabd.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %[[SEL]], <vscale x 4 x float> %op2)
489+
// CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
490+
return SVE_ACLE_FUNC(svabd,_f32,_z,)(pg, op1, op2);
491+
}
492+
493+
svfloat64_t test_svabd_f64_z(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
494+
{
495+
// CHECK-LABEL: test_svabd_f64_z
496+
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
497+
// CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.sel.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> zeroinitializer)
498+
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fabd.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %[[SEL]], <vscale x 2 x double> %op2)
499+
// CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
500+
return SVE_ACLE_FUNC(svabd,_f64,_z,)(pg, op1, op2);
501+
}
502+
503+
svfloat16_t test_svabd_f16_m(svbool_t pg, svfloat16_t op1, svfloat16_t op2)
504+
{
505+
// CHECK-LABEL: test_svabd_f16_m
506+
// CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
507+
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fabd.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> %op2)
508+
// CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
509+
return SVE_ACLE_FUNC(svabd,_f16,_m,)(pg, op1, op2);
510+
}
511+
512+
svfloat32_t test_svabd_f32_m(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
513+
{
514+
// CHECK-LABEL: test_svabd_f32_m
515+
// CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
516+
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fabd.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> %op2)
517+
// CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
518+
return SVE_ACLE_FUNC(svabd,_f32,_m,)(pg, op1, op2);
519+
}
520+
521+
svfloat64_t test_svabd_f64_m(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
522+
{
523+
// CHECK-LABEL: test_svabd_f64_m
524+
// CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
525+
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fabd.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> %op2)
526+
// CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
527+
return SVE_ACLE_FUNC(svabd,_f64,_m,)(pg, op1, op2);
528+
}
529+
530+
svfloat16_t test_svabd_f16_x(svbool_t pg, svfloat16_t op1, svfloat16_t op2)
531+
{
532+
// CHECK-LABEL: test_svabd_f16_x
533+
// CHECK: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
534+
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fabd.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> %op2)
535+
// CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
536+
return SVE_ACLE_FUNC(svabd,_f16,_x,)(pg, op1, op2);
537+
}
538+
539+
svfloat32_t test_svabd_f32_x(svbool_t pg, svfloat32_t op1, svfloat32_t op2)
540+
{
541+
// CHECK-LABEL: test_svabd_f32_x
542+
// CHECK: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
543+
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fabd.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> %op2)
544+
// CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
545+
return SVE_ACLE_FUNC(svabd,_f32,_x,)(pg, op1, op2);
546+
}
547+
548+
svfloat64_t test_svabd_f64_x(svbool_t pg, svfloat64_t op1, svfloat64_t op2)
549+
{
550+
// CHECK-LABEL: test_svabd_f64_x
551+
// CHECK: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
552+
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fabd.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> %op2)
553+
// CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
554+
return SVE_ACLE_FUNC(svabd,_f64,_x,)(pg, op1, op2);
555+
}
556+
557+
svfloat16_t test_svabd_n_f16_z(svbool_t pg, svfloat16_t op1, float16_t op2)
558+
{
559+
// CHECK-LABEL: test_svabd_n_f16_z
560+
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
561+
// CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %op2)
562+
// CHECK-DAG: %[[SEL:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.sel.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> zeroinitializer)
563+
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fabd.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %[[SEL]], <vscale x 8 x half> %[[DUP]])
564+
// CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
565+
return SVE_ACLE_FUNC(svabd,_n_f16,_z,)(pg, op1, op2);
566+
}
567+
568+
svfloat32_t test_svabd_n_f32_z(svbool_t pg, svfloat32_t op1, float32_t op2)
569+
{
570+
// CHECK-LABEL: test_svabd_n_f32_z
571+
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
572+
// CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %op2)
573+
// CHECK-DAG: %[[SEL:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.sel.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> zeroinitializer)
574+
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fabd.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %[[SEL]], <vscale x 4 x float> %[[DUP]])
575+
// CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
576+
return SVE_ACLE_FUNC(svabd,_n_f32,_z,)(pg, op1, op2);
577+
}
578+
579+
svfloat64_t test_svabd_n_f64_z(svbool_t pg, svfloat64_t op1, float64_t op2)
580+
{
581+
// CHECK-LABEL: test_svabd_n_f64_z
582+
// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
583+
// CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %op2)
584+
// CHECK-DAG: %[[SEL:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.sel.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> zeroinitializer)
585+
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fabd.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %[[SEL]], <vscale x 2 x double> %[[DUP]])
586+
// CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
587+
return SVE_ACLE_FUNC(svabd,_n_f64,_z,)(pg, op1, op2);
588+
}
589+
590+
svfloat16_t test_svabd_n_f16_m(svbool_t pg, svfloat16_t op1, float16_t op2)
591+
{
592+
// CHECK-LABEL: test_svabd_n_f16_m
593+
// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
594+
// CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %op2)
595+
// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fabd.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> %[[DUP]])
596+
// CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
597+
return SVE_ACLE_FUNC(svabd,_n_f16,_m,)(pg, op1, op2);
598+
}
599+
600+
svfloat32_t test_svabd_n_f32_m(svbool_t pg, svfloat32_t op1, float32_t op2)
601+
{
602+
// CHECK-LABEL: test_svabd_n_f32_m
603+
// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
604+
// CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %op2)
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// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fabd.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> %[[DUP]])
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// CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
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return SVE_ACLE_FUNC(svabd,_n_f32,_m,)(pg, op1, op2);
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}
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svfloat64_t test_svabd_n_f64_m(svbool_t pg, svfloat64_t op1, float64_t op2)
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{
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// CHECK-LABEL: test_svabd_n_f64_m
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// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
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// CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %op2)
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// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fabd.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> %[[DUP]])
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// CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
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return SVE_ACLE_FUNC(svabd,_n_f64,_m,)(pg, op1, op2);
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}
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svfloat16_t test_svabd_n_f16_x(svbool_t pg, svfloat16_t op1, float16_t op2)
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{
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// CHECK-LABEL: test_svabd_n_f16_x
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// CHECK-DAG: %[[PG:.*]] = call <vscale x 8 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv8i1(<vscale x 16 x i1> %pg)
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// CHECK-DAG: %[[DUP:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.dup.x.nxv8f16(half %op2)
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// CHECK: %[[INTRINSIC:.*]] = call <vscale x 8 x half> @llvm.aarch64.sve.fabd.nxv8f16(<vscale x 8 x i1> %[[PG]], <vscale x 8 x half> %op1, <vscale x 8 x half> %[[DUP]])
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// CHECK: ret <vscale x 8 x half> %[[INTRINSIC]]
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return SVE_ACLE_FUNC(svabd,_n_f16,_x,)(pg, op1, op2);
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}
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svfloat32_t test_svabd_n_f32_x(svbool_t pg, svfloat32_t op1, float32_t op2)
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{
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// CHECK-LABEL: test_svabd_n_f32_x
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// CHECK-DAG: %[[PG:.*]] = call <vscale x 4 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv4i1(<vscale x 16 x i1> %pg)
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// CHECK-DAG: %[[DUP:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.dup.x.nxv4f32(float %op2)
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// CHECK: %[[INTRINSIC:.*]] = call <vscale x 4 x float> @llvm.aarch64.sve.fabd.nxv4f32(<vscale x 4 x i1> %[[PG]], <vscale x 4 x float> %op1, <vscale x 4 x float> %[[DUP]])
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// CHECK: ret <vscale x 4 x float> %[[INTRINSIC]]
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return SVE_ACLE_FUNC(svabd,_n_f32,_x,)(pg, op1, op2);
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}
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svfloat64_t test_svabd_n_f64_x(svbool_t pg, svfloat64_t op1, float64_t op2)
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{
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// CHECK-LABEL: test_svabd_n_f64_x
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// CHECK-DAG: %[[PG:.*]] = call <vscale x 2 x i1> @llvm.aarch64.sve.convert.from.svbool.nxv2i1(<vscale x 16 x i1> %pg)
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// CHECK-DAG: %[[DUP:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.dup.x.nxv2f64(double %op2)
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// CHECK: %[[INTRINSIC:.*]] = call <vscale x 2 x double> @llvm.aarch64.sve.fabd.nxv2f64(<vscale x 2 x i1> %[[PG]], <vscale x 2 x double> %op1, <vscale x 2 x double> %[[DUP]])
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// CHECK: ret <vscale x 2 x double> %[[INTRINSIC]]
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return SVE_ACLE_FUNC(svabd,_n_f64,_x,)(pg, op1, op2);
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}

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