@@ -43,3 +43,179 @@ define <vscale x 2 x i64> @udiv_i64(<vscale x 2 x i64> %a, <vscale x 2 x i64> %b
4343 %div = udiv <vscale x 2 x i64 > %a , %b
4444 ret <vscale x 2 x i64 > %div
4545}
46+
47+ ;
48+ ; SMIN
49+ ;
50+
51+ define <vscale x 16 x i8 > @smin_i8 (<vscale x 16 x i8 > %a , <vscale x 16 x i8 > %b , <vscale x 16 x i8 > %c ) {
52+ ; CHECK-LABEL: @smin_i8
53+ ; CHECK-DAG: ptrue p0.b
54+ ; CHECK-DAG: smin z0.b, p0/m, z0.b, z1.b
55+ ; CHECK-NEXT: ret
56+ %cmp = icmp slt <vscale x 16 x i8 > %a , %b
57+ %min = select <vscale x 16 x i1 > %cmp , <vscale x 16 x i8 > %a , <vscale x 16 x i8 > %b
58+ ret <vscale x 16 x i8 > %min
59+ }
60+
61+ define <vscale x 8 x i16 > @smin_i16 (<vscale x 8 x i16 > %a , <vscale x 8 x i16 > %b , <vscale x 8 x i16 > %c ) {
62+ ; CHECK-LABEL: @smin_i16
63+ ; CHECK-DAG: ptrue p0.h
64+ ; CHECK-DAG: smin z0.h, p0/m, z0.h, z1.h
65+ ; CHECK-NEXT: ret
66+ %cmp = icmp slt <vscale x 8 x i16 > %a , %b
67+ %min = select <vscale x 8 x i1 > %cmp , <vscale x 8 x i16 > %a , <vscale x 8 x i16 > %b
68+ ret <vscale x 8 x i16 > %min
69+ }
70+
71+ define <vscale x 4 x i32 > @smin_i32 (<vscale x 4 x i32 > %a , <vscale x 4 x i32 > %b , <vscale x 4 x i32 > %c ) {
72+ ; CHECK-LABEL: smin_i32:
73+ ; CHECK-DAG: ptrue p0.s
74+ ; CHECK-DAG: smin z0.s, p0/m, z0.s, z1.s
75+ ; CHECK-NEXT: ret
76+ %cmp = icmp slt <vscale x 4 x i32 > %a , %b
77+ %min = select <vscale x 4 x i1 > %cmp , <vscale x 4 x i32 > %a , <vscale x 4 x i32 > %b
78+ ret <vscale x 4 x i32 > %min
79+ }
80+
81+ define <vscale x 2 x i64 > @smin_i64 (<vscale x 2 x i64 > %a , <vscale x 2 x i64 > %b , <vscale x 2 x i64 > %c ) {
82+ ; CHECK-LABEL: smin_i64:
83+ ; CHECK-DAG: ptrue p0.d
84+ ; CHECK-DAG: smin z0.d, p0/m, z0.d, z1.d
85+ ; CHECK-NEXT: ret
86+ %cmp = icmp slt <vscale x 2 x i64 > %a , %b
87+ %min = select <vscale x 2 x i1 > %cmp , <vscale x 2 x i64 > %a , <vscale x 2 x i64 > %b
88+ ret <vscale x 2 x i64 > %min
89+ }
90+
91+ ;
92+ ; UMIN
93+ ;
94+
95+ define <vscale x 16 x i8 > @umin_i8 (<vscale x 16 x i8 > %a , <vscale x 16 x i8 > %b , <vscale x 16 x i8 > %c ) {
96+ ; CHECK-LABEL: @umin_i8
97+ ; CHECK-DAG: ptrue p0.b
98+ ; CHECK-DAG: umin z0.b, p0/m, z0.b, z1.b
99+ ; CHECK-NEXT: ret
100+ %cmp = icmp ult <vscale x 16 x i8 > %a , %b
101+ %min = select <vscale x 16 x i1 > %cmp , <vscale x 16 x i8 > %a , <vscale x 16 x i8 > %b
102+ ret <vscale x 16 x i8 > %min
103+ }
104+
105+ define <vscale x 8 x i16 > @umin_i16 (<vscale x 8 x i16 > %a , <vscale x 8 x i16 > %b , <vscale x 8 x i16 > %c ) {
106+ ; CHECK-LABEL: @umin_i16
107+ ; CHECK-DAG: ptrue p0.h
108+ ; CHECK-DAG: umin z0.h, p0/m, z0.h, z1.h
109+ ; CHECK-NEXT: ret
110+ %cmp = icmp ult <vscale x 8 x i16 > %a , %b
111+ %min = select <vscale x 8 x i1 > %cmp , <vscale x 8 x i16 > %a , <vscale x 8 x i16 > %b
112+ ret <vscale x 8 x i16 > %min
113+ }
114+
115+ define <vscale x 4 x i32 > @umin_i32 (<vscale x 4 x i32 > %a , <vscale x 4 x i32 > %b , <vscale x 4 x i32 > %c ) {
116+ ; CHECK-LABEL: umin_i32:
117+ ; CHECK-DAG: ptrue p0.s
118+ ; CHECK-DAG: umin z0.s, p0/m, z0.s, z1.s
119+ ; CHECK-NEXT: ret
120+ %cmp = icmp ult <vscale x 4 x i32 > %a , %b
121+ %min = select <vscale x 4 x i1 > %cmp , <vscale x 4 x i32 > %a , <vscale x 4 x i32 > %b
122+ ret <vscale x 4 x i32 > %min
123+ }
124+
125+ define <vscale x 2 x i64 > @umin_i64 (<vscale x 2 x i64 > %a , <vscale x 2 x i64 > %b , <vscale x 2 x i64 > %c ) {
126+ ; CHECK-LABEL: umin_i64:
127+ ; CHECK-DAG: ptrue p0.d
128+ ; CHECK-DAG: umin z0.d, p0/m, z0.d, z1.d
129+ ; CHECK-NEXT: ret
130+ %cmp = icmp ult <vscale x 2 x i64 > %a , %b
131+ %min = select <vscale x 2 x i1 > %cmp , <vscale x 2 x i64 > %a , <vscale x 2 x i64 > %b
132+ ret <vscale x 2 x i64 > %min
133+ }
134+
135+ ;
136+ ; SMAX
137+ ;
138+
139+ define <vscale x 16 x i8 > @smax_i8 (<vscale x 16 x i8 > %a , <vscale x 16 x i8 > %b , <vscale x 16 x i8 > %c ) {
140+ ; CHECK-LABEL: @smax_i8
141+ ; CHECK-DAG: ptrue p0.b
142+ ; CHECK-DAG: smax z0.b, p0/m, z0.b, z1.b
143+ ; CHECK-NEXT: ret
144+ %cmp = icmp sgt <vscale x 16 x i8 > %a , %b
145+ %min = select <vscale x 16 x i1 > %cmp , <vscale x 16 x i8 > %a , <vscale x 16 x i8 > %b
146+ ret <vscale x 16 x i8 > %min
147+ }
148+
149+ define <vscale x 8 x i16 > @smax_i16 (<vscale x 8 x i16 > %a , <vscale x 8 x i16 > %b , <vscale x 8 x i16 > %c ) {
150+ ; CHECK-LABEL: @smax_i16
151+ ; CHECK-DAG: ptrue p0.h
152+ ; CHECK-DAG: smax z0.h, p0/m, z0.h, z1.h
153+ ; CHECK-NEXT: ret
154+ %cmp = icmp sgt <vscale x 8 x i16 > %a , %b
155+ %min = select <vscale x 8 x i1 > %cmp , <vscale x 8 x i16 > %a , <vscale x 8 x i16 > %b
156+ ret <vscale x 8 x i16 > %min
157+ }
158+
159+ define <vscale x 4 x i32 > @smax_i32 (<vscale x 4 x i32 > %a , <vscale x 4 x i32 > %b , <vscale x 4 x i32 > %c ) {
160+ ; CHECK-LABEL: smax_i32:
161+ ; CHECK-DAG: ptrue p0.s
162+ ; CHECK-DAG: smax z0.s, p0/m, z0.s, z1.s
163+ ; CHECK-NEXT: ret
164+ %cmp = icmp sgt <vscale x 4 x i32 > %a , %b
165+ %min = select <vscale x 4 x i1 > %cmp , <vscale x 4 x i32 > %a , <vscale x 4 x i32 > %b
166+ ret <vscale x 4 x i32 > %min
167+ }
168+
169+ define <vscale x 2 x i64 > @smax_i64 (<vscale x 2 x i64 > %a , <vscale x 2 x i64 > %b , <vscale x 2 x i64 > %c ) {
170+ ; CHECK-LABEL: smax_i64:
171+ ; CHECK-DAG: ptrue p0.d
172+ ; CHECK-DAG: smax z0.d, p0/m, z0.d, z1.d
173+ ; CHECK-NEXT: ret
174+ %cmp = icmp sgt <vscale x 2 x i64 > %a , %b
175+ %min = select <vscale x 2 x i1 > %cmp , <vscale x 2 x i64 > %a , <vscale x 2 x i64 > %b
176+ ret <vscale x 2 x i64 > %min
177+ }
178+
179+ ;
180+ ; UMAX
181+ ;
182+
183+ define <vscale x 16 x i8 > @umax_i8 (<vscale x 16 x i8 > %a , <vscale x 16 x i8 > %b , <vscale x 16 x i8 > %c ) {
184+ ; CHECK-LABEL: @umax_i8
185+ ; CHECK-DAG: ptrue p0.b
186+ ; CHECK-DAG: umax z0.b, p0/m, z0.b, z1.b
187+ ; CHECK-NEXT: ret
188+ %cmp = icmp ugt <vscale x 16 x i8 > %a , %b
189+ %min = select <vscale x 16 x i1 > %cmp , <vscale x 16 x i8 > %a , <vscale x 16 x i8 > %b
190+ ret <vscale x 16 x i8 > %min
191+ }
192+
193+ define <vscale x 8 x i16 > @umax_i16 (<vscale x 8 x i16 > %a , <vscale x 8 x i16 > %b , <vscale x 8 x i16 > %c ) {
194+ ; CHECK-LABEL: @umax_i16
195+ ; CHECK-DAG: ptrue p0.h
196+ ; CHECK-DAG: umax z0.h, p0/m, z0.h, z1.h
197+ ; CHECK-NEXT: ret
198+ %cmp = icmp ugt <vscale x 8 x i16 > %a , %b
199+ %min = select <vscale x 8 x i1 > %cmp , <vscale x 8 x i16 > %a , <vscale x 8 x i16 > %b
200+ ret <vscale x 8 x i16 > %min
201+ }
202+
203+ define <vscale x 4 x i32 > @umax_i32 (<vscale x 4 x i32 > %a , <vscale x 4 x i32 > %b , <vscale x 4 x i32 > %c ) {
204+ ; CHECK-LABEL: umax_i32:
205+ ; CHECK-DAG: ptrue p0.s
206+ ; CHECK-DAG: umax z0.s, p0/m, z0.s, z1.s
207+ ; CHECK-NEXT: ret
208+ %cmp = icmp ugt <vscale x 4 x i32 > %a , %b
209+ %min = select <vscale x 4 x i1 > %cmp , <vscale x 4 x i32 > %a , <vscale x 4 x i32 > %b
210+ ret <vscale x 4 x i32 > %min
211+ }
212+
213+ define <vscale x 2 x i64 > @umax_i64 (<vscale x 2 x i64 > %a , <vscale x 2 x i64 > %b , <vscale x 2 x i64 > %c ) {
214+ ; CHECK-LABEL: umax_i64:
215+ ; CHECK-DAG: ptrue p0.d
216+ ; CHECK-DAG: umax z0.d, p0/m, z0.d, z1.d
217+ ; CHECK-NEXT: ret
218+ %cmp = icmp ugt <vscale x 2 x i64 > %a , %b
219+ %min = select <vscale x 2 x i1 > %cmp , <vscale x 2 x i64 > %a , <vscale x 2 x i64 > %b
220+ ret <vscale x 2 x i64 > %min
221+ }
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