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[VPlan] Move printing final VPlan to ::execute (NFC).
This moves printing of the final VPlan to ::execute. This ensures the final VPlan is printed, including recipes that get introduced by late, lowering transforms and skeleton construction. Split off from llvm#114292, to simplify the diff.
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7 files changed

+78
-71
lines changed

7 files changed

+78
-71
lines changed

‎llvm/lib/Transforms/Vectorize/LoopVectorize.cpp

Lines changed: 0 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -7678,11 +7678,6 @@ DenseMap<const SCEV *, Value *> LoopVectorizationPlanner::executePlan(
76787678
OrigLoop->getHeader()->getContext());
76797679
VPlanTransforms::optimizeForVFAndUF(BestVPlan, BestVF, BestUF, PSE);
76807680

7681-
LLVM_DEBUG(dbgs() << "Executing best plan with VF=" << BestVF
7682-
<< ", UF=" << BestUF << '\n');
7683-
BestVPlan.setName("Final VPlan");
7684-
LLVM_DEBUG(BestVPlan.dump());
7685-
76867681
// Perform the actual loop transformation.
76877682
VPTransformState State(&TTI, BestVF, BestUF, LI, DT, ILV.Builder, &ILV,
76887683
&BestVPlan);

‎llvm/lib/Transforms/Vectorize/VPlan.cpp

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1015,6 +1015,11 @@ void VPlan::execute(VPTransformState *State) {
10151015
replaceVPBBWithIRVPBB(getScalarPreheader(), ScalarPh);
10161016
replaceVPBBWithIRVPBB(MiddleVPBB, MiddleBB);
10171017

1018+
LLVM_DEBUG(dbgs() << "Executing best plan with VF=" << State->VF
1019+
<< ", UF=" << getUF() << '\n');
1020+
setName("Final VPlan");
1021+
LLVM_DEBUG(dump());
1022+
10181023
// Disconnect the middle block from its single successor (the scalar loop
10191024
// header) in both the CFG and DT. The branch will be recreated during VPlan
10201025
// execution.

‎llvm/lib/Transforms/Vectorize/VPlanRecipes.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -3496,7 +3496,7 @@ void VPScalarPHIRecipe::execute(VPTransformState &State) {
34963496
#if !defined(NDEBUG) || defined(LLVM_ENABLE_DUMP)
34973497
void VPScalarPHIRecipe::print(raw_ostream &O, const Twine &Indent,
34983498
VPSlotTracker &SlotTracker) const {
3499-
O << Indent << "SCALAR-PHI";
3499+
O << Indent << "SCALAR-PHI ";
35003500
printAsOperand(O, SlotTracker);
35013501
O << " = phi ";
35023502
printOperands(O, SlotTracker);

‎llvm/test/Transforms/LoopVectorize/RISCV/riscv-vector-reverse.ll

Lines changed: 40 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -142,11 +142,11 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
142142
; CHECK-NEXT: LV: Interleaving is not beneficial.
143143
; CHECK-NEXT: LV: Found a vectorizable loop (vscale x 4) in <stdin>
144144
; CHECK-NEXT: LEV: Epilogue vectorization is not profitable for this loop
145-
; CHECK-NEXT: Executing best plan with VF=vscale x 4, UF=1
145+
; CHECK: Executing best plan with VF=vscale x 4, UF=1
146146
; CHECK-NEXT: VPlan 'Final VPlan for VF={vscale x 4},UF={1}' {
147-
; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF
148-
; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF
149-
; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count
147+
; CHECK-NEXT: Live-in ir<[[VF:%.+]]> = VF
148+
; CHECK-NEXT: Live-in ir<[[VFxUF:%.+]]>.1 = VF * UF
149+
; CHECK-NEXT: Live-in ir<[[VEC_TC:%.+]]> = vector-trip-count
150150
; CHECK-NEXT: vp<[[TC:%.+]]> = original trip-count
151151
; CHECK-EMPTY:
152152
; CHECK-NEXT: ir-bb<for.body.preheader>:
@@ -159,35 +159,37 @@ define void @vector_reverse_i64(ptr nocapture noundef writeonly %A, ptr nocaptur
159159
; CHECK-EMPTY:
160160
; CHECK-NEXT: <x1> vector loop: {
161161
; CHECK-NEXT: vector.body:
162-
; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
162+
; CHECK-NEXT: SCALAR-PHI vp<[[CAN_IV:%.+]]> = phi ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
163163
; CHECK-NEXT: vp<[[DEV_IV:%.+]]> = DERIVED-IV ir<%n> + vp<[[CAN_IV]]> * ir<-1>
164164
; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[DEV_IV]]>, ir<-1>
165165
; CHECK-NEXT: CLONE ir<%i.0> = add nsw vp<[[STEPS]]>, ir<-1>
166166
; CHECK-NEXT: CLONE ir<%idxprom> = zext ir<%i.0>
167167
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%B>, ir<%idxprom>
168-
; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = reverse-vector-pointer inbounds ir<%arrayidx>, vp<[[VF]]>
169-
; CHECK-NEXT: WIDEN ir<%13> = load vp<[[VEC_PTR]]>
170-
; CHECK-NEXT: WIDEN ir<%add9> = add ir<%13>, ir<1>
168+
; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = reverse-vector-pointer inbounds ir<%arrayidx>, ir<[[VF]]>
169+
; CHECK-NEXT: WIDEN ir<[[L:%.+]]> = load vp<[[VEC_PTR]]>
170+
; CHECK-NEXT: WIDEN ir<%add9> = add ir<[[L]]>, ir<1>
171171
; CHECK-NEXT: CLONE ir<%arrayidx3> = getelementptr inbounds ir<%A>, ir<%idxprom>
172-
; CHECK-NEXT: vp<[[VEC_PTR2:%.+]]> = reverse-vector-pointer inbounds ir<%arrayidx3>, vp<[[VF]]>
172+
; CHECK-NEXT: vp<[[VEC_PTR2:%.+]]> = reverse-vector-pointer inbounds ir<%arrayidx3>, ir<[[VF]]>
173173
; CHECK-NEXT: WIDEN store vp<[[VEC_PTR2]]>, ir<%add9>
174-
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>
175-
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]>
174+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, ir<[[VFxUF]]>.1
175+
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, ir<[[VEC_TC]]>
176176
; CHECK-NEXT: No successors
177177
; CHECK-NEXT: }
178-
; CHECK-NEXT: Successor(s): middle.block
178+
; CHECK-NEXT: Successor(s): ir-bb<middle.block>
179179
; CHECK-EMPTY:
180-
; CHECK-NEXT: middle.block:
181-
; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq vp<[[TC]]>, vp<[[VEC_TC]]>
180+
; CHECK-NEXT: ir-bb<middle.block>:
181+
; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq vp<[[TC]]>, ir<[[VEC_TC]]>
182182
; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]>
183-
; CHECK-NEXT: Successor(s): ir-bb<for.cond.cleanup.loopexit>, scalar.ph
183+
; CHECK-NEXT: Successor(s): ir-bb<for.cond.cleanup.loopexit>, ir-bb<scalar.ph>
184184
; CHECK-EMPTY:
185-
; CHECK-NEXT: scalar.ph:
185+
; CHECK-NEXT: ir-bb<scalar.ph>:
186+
; CHECK-NEXT: EMIT vp<[[RESUME1:%.+]]> = resume-phi ir<%ind.end>, ir<%0>
187+
; CHECK-NEXT: EMIT vp<[[RESUME2:%.+]]>.1 = resume-phi ir<%ind.end3>, ir<%n>
186188
; CHECK-NEXT: Successor(s): ir-bb<for.body>
187189
; CHECK-EMPTY:
188190
; CHECK-NEXT: ir-bb<for.body>:
189-
; CHECK-NEXT: IR %indvars.iv = phi i64 [ %0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
190-
; CHECK-NEXT: IR %i.0.in8 = phi i32 [ %n, %for.body.preheader ], [ %i.0, %for.body ]
191+
; CHECK-NEXT: IR %indvars.iv = phi i64 [ %0, %scalar.ph ], [ %indvars.iv.next, %for.body ] (extra operand: vp<[[RESUME1]]> from ir-bb<scalar.ph>
192+
; CHECK-NEXT: IR %i.0.in8 = phi i32 [ %n, %scalar.ph ], [ %i.0, %for.body ] (extra operand: vp<[[RESUME2]]>.1 from ir-bb<scalar.ph>
191193
; CHECK: IR %indvars.iv.next = add nsw i64 %indvars.iv, -1
192194
; CHECK-NEXT: No successors
193195
; CHECK-EMPTY:
@@ -356,11 +358,11 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
356358
; CHECK-NEXT: LV: Interleaving is not beneficial.
357359
; CHECK-NEXT: LV: Found a vectorizable loop (vscale x 4) in <stdin>
358360
; CHECK-NEXT: LEV: Epilogue vectorization is not profitable for this loop
359-
; CHECK-NEXT: Executing best plan with VF=vscale x 4, UF=1
361+
; CHECK: Executing best plan with VF=vscale x 4, UF=1
360362
; CHECK-NEXT: VPlan 'Final VPlan for VF={vscale x 4},UF={1}' {
361-
; CHECK-NEXT: Live-in vp<[[VF:%.+]]> = VF
362-
; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF
363-
; CHECK-NEXT: Live-in vp<[[VEC_TC:%.+]]> = vector-trip-count
363+
; CHECK-NEXT: Live-in ir<[[VF:%.+]]> = VF
364+
; CHECK-NEXT: Live-in ir<[[VFxUF:%.+]]>.1 = VF * UF
365+
; CHECK-NEXT: Live-in ir<[[VEC_TC:%.+]]> = vector-trip-count
364366
; CHECK-NEXT: vp<[[TC:%.+]]> = original trip-count
365367
; CHECK-EMPTY:
366368
; CHECK-NEXT: ir-bb<for.body.preheader>:
@@ -373,35 +375,37 @@ define void @vector_reverse_f32(ptr nocapture noundef writeonly %A, ptr nocaptur
373375
; CHECK-EMPTY:
374376
; CHECK-NEXT: <x1> vector loop: {
375377
; CHECK-NEXT: vector.body:
376-
; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION
378+
; CHECK-NEXT: SCALAR-PHI vp<[[CAN_IV:%.+]]> = phi ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
377379
; CHECK-NEXT: vp<[[DEV_IV:%.+]]> = DERIVED-IV ir<%n> + vp<[[CAN_IV]]> * ir<-1>
378380
; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[DEV_IV]]>, ir<-1>
379381
; CHECK-NEXT: CLONE ir<%i.0> = add nsw vp<[[STEPS]]>, ir<-1>
380382
; CHECK-NEXT: CLONE ir<%idxprom> = zext ir<%i.0>
381383
; CHECK-NEXT: CLONE ir<%arrayidx> = getelementptr inbounds ir<%B>, ir<%idxprom>
382-
; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = reverse-vector-pointer inbounds ir<%arrayidx>, vp<[[VF]]>
383-
; CHECK-NEXT: WIDEN ir<%13> = load vp<[[VEC_PTR]]>
384-
; CHECK-NEXT: WIDEN ir<%conv1> = fadd ir<%13>, ir<1.000000e+00>
384+
; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = reverse-vector-pointer inbounds ir<%arrayidx>, ir<[[VF]]>
385+
; CHECK-NEXT: WIDEN ir<[[L:%.+]]> = load vp<[[VEC_PTR]]>
386+
; CHECK-NEXT: WIDEN ir<%conv1> = fadd ir<[[L]]>, ir<1.000000e+00>
385387
; CHECK-NEXT: CLONE ir<%arrayidx3> = getelementptr inbounds ir<%A>, ir<%idxprom>
386-
; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = reverse-vector-pointer inbounds ir<%arrayidx3>, vp<[[VF]]>
388+
; CHECK-NEXT: vp<[[VEC_PTR:%.+]]> = reverse-vector-pointer inbounds ir<%arrayidx3>, ir<[[VF]]>
387389
; CHECK-NEXT: WIDEN store vp<[[VEC_PTR]]>, ir<%conv1>
388-
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT:%.+]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>
389-
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VEC_TC]]>
390+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, ir<[[VFxUF]]>.1
391+
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, ir<[[VEC_TC]]>
390392
; CHECK-NEXT: No successors
391393
; CHECK-NEXT: }
392-
; CHECK-NEXT: Successor(s): middle.block
394+
; CHECK-NEXT: Successor(s): ir-bb<middle.block>
393395
; CHECK-EMPTY:
394-
; CHECK-NEXT: middle.block:
395-
; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq vp<[[TC]]>, vp<[[VEC_TC]]>
396+
; CHECK-NEXT: ir-bb<middle.block>:
397+
; CHECK-NEXT: EMIT vp<[[CMP:%.+]]> = icmp eq vp<[[TC]]>, ir<[[VEC_TC]]>
396398
; CHECK-NEXT: EMIT branch-on-cond vp<[[CMP]]>
397-
; CHECK-NEXT: Successor(s): ir-bb<for.cond.cleanup.loopexit>, scalar.ph
399+
; CHECK-NEXT: Successor(s): ir-bb<for.cond.cleanup.loopexit>, ir-bb<scalar.ph>
398400
; CHECK-EMPTY:
399-
; CHECK-NEXT: scalar.ph:
401+
; CHECK-NEXT: ir-bb<scalar.ph>:
402+
; CHECK-NEXT: EMIT vp<[[RESUME1:%.+]]> = resume-phi ir<%ind.end>, ir<%0>
403+
; CHECK-NEXT: EMIT vp<[[RESUME2:%.+]]>.1 = resume-phi ir<%ind.end3>, ir<%n>
400404
; CHECK-NEXT: Successor(s): ir-bb<for.body>
401405
; CHECK-EMPTY:
402406
; CHECK-NEXT: ir-bb<for.body>:
403-
; CHECK-NEXT: IR %indvars.iv = phi i64 [ %0, %for.body.preheader ], [ %indvars.iv.next, %for.body ]
404-
; CHECK-NEXT: IR %i.0.in8 = phi i32 [ %n, %for.body.preheader ], [ %i.0, %for.body ]
407+
; CHECK-NEXT: IR %indvars.iv = phi i64 [ %0, %scalar.ph ], [ %indvars.iv.next, %for.body ] (extra operand: vp<[[RESUME1]]> from ir-bb<scalar.ph>
408+
; CHECK-NEXT: IR %i.0.in8 = phi i32 [ %n, %scalar.ph ], [ %i.0, %for.body ] (extra operand: vp<[[RESUME2]]>.1 from ir-bb<scalar.ph>
405409
; CHECK: IR %indvars.iv.next = add nsw i64 %indvars.iv, -1
406410
; CHECK-NEXT: No successors
407411
; CHECK-EMPTY:

‎llvm/test/Transforms/LoopVectorize/RISCV/vplan-vp-select-intrinsics.ll

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -7,17 +7,17 @@
77

88
define void @vp_select(ptr noalias %a, ptr noalias %b, ptr noalias %c, i64 %N) {
99
; IF-EVL: VPlan 'Final VPlan for VF={vscale x 1,vscale x 2,vscale x 4},UF={1}' {
10-
; IF-EVL-NEXT: Live-in vp<[[VFUF:%[0-9]+]]> = VF * UF
11-
; IF-EVL-NEXT: Live-in vp<[[VTC:%[0-9]+]]> = vector-trip-count
10+
; IF-EVL-NEXT: Live-in ir<[[VFUF:%.+]]> = VF * UF
11+
; IF-EVL-NEXT: Live-in ir<[[VTC:%.+]]> = vector-trip-count
1212
; IF-EVL-NEXT: Live-in ir<%N> = original trip-count
1313

1414
; IF-EVL: vector.ph:
1515
; IF-EVL-NEXT: Successor(s): vector loop
1616

1717
; IF-EVL: <x1> vector loop: {
1818
; IF-EVL-NEXT: vector.body:
19-
; IF-EVL-NEXT: EMIT vp<[[IV:%[0-9]+]]> = CANONICAL-INDUCTION
20-
; IF-EVL-NEXT: EXPLICIT-VECTOR-LENGTH-BASED-IV-PHI vp<[[EVL_PHI:%[0-9]+]]> = phi ir<0>, vp<[[IV_NEX:%.+]]>
19+
; IF-EVL-NEXT: SCALAR-PHI vp<[[IV:%[0-9]+]]> = phi ir<0>, vp<[[IV_NEXT_EXIT:%.+]]>
20+
; IF-EVL-NEXT: SCALAR-PHI vp<[[EVL_PHI:%[0-9]+]]> = phi ir<0>, vp<[[IV_NEX:%.+]]>
2121
; IF-EVL-NEXT: EMIT vp<[[AVL:%.+]]> = sub ir<%N>, vp<[[EVL_PHI]]>
2222
; IF-EVL-NEXT: EMIT vp<[[EVL:%.+]]> = EXPLICIT-VECTOR-LENGTH vp<[[AVL]]>
2323
; IF-EVL-NEXT: vp<[[ST:%[0-9]+]]> = SCALAR-STEPS vp<[[EVL_PHI]]>, ir<1>
@@ -29,15 +29,15 @@
2929
; IF-EVL-NEXT: WIDEN ir<[[LD2:%.+]]> = vp.load vp<[[PTR2]]>, vp<[[EVL]]>
3030
; IF-EVL-NEXT: WIDEN ir<[[CMP:%.+]]> = icmp sgt ir<[[LD1]]>, ir<[[LD2]]>
3131
; IF-EVL-NEXT: WIDEN ir<[[SUB:%.+]]> = vp.sub ir<0>, ir<[[LD2]]>, vp<[[EVL]]>
32-
; IF-EVL-NEXT: WIDEN-INTRINSIC vp<[[SELECT:%.+]]> = call llvm.vp.select(ir<[[CMP]]>, ir<%1>, ir<%2>, vp<[[EVL]]>)
32+
; IF-EVL-NEXT: WIDEN-INTRINSIC vp<[[SELECT:%.+]]> = call llvm.vp.select(ir<[[CMP]]>, ir<[[LD2]]>, ir<[[SUB]]>, vp<[[EVL]]>)
3333
; IF-EVL-NEXT: WIDEN ir<[[ADD:%.+]]> = vp.add vp<[[SELECT]]>, ir<[[LD1]]>, vp<[[EVL]]>
3434
; IF-EVL-NEXT: CLONE ir<[[GEP3:%.+]]> = getelementptr inbounds ir<%a>, vp<[[ST]]>
3535
; IF-EVL-NEXT: vp<[[PTR3:%.+]]> = vector-pointer ir<[[GEP3]]>
3636
; IF-EVL-NEXT: WIDEN vp.store vp<[[PTR3]]>, ir<[[ADD]]>, vp<[[EVL]]>
3737
; IF-EVL-NEXT: SCALAR-CAST vp<[[CAST:%[0-9]+]]> = zext vp<[[EVL]]> to i64
3838
; IF-EVL-NEXT: EMIT vp<[[IV_NEX]]> = add vp<[[CAST]]>, vp<[[EVL_PHI]]>
39-
; IF-EVL-NEXT: EMIT vp<[[IV_NEXT_EXIT:%.+]]> = add vp<[[IV]]>, vp<[[VFUF]]>
40-
; IF-EVL-NEXT: EMIT branch-on-count vp<[[IV_NEXT_EXIT]]>, vp<[[VTC]]>
39+
; IF-EVL-NEXT: EMIT vp<[[IV_NEXT_EXIT]]> = add vp<[[IV]]>, ir<[[VFUF]]>
40+
; IF-EVL-NEXT: EMIT branch-on-count vp<[[IV_NEXT_EXIT]]>, ir<[[VTC]]>
4141
; IF-EVL-NEXT: No successors
4242
; IF-EVL-NEXT: }
4343

‎llvm/test/Transforms/LoopVectorize/vplan-predicate-switch.ll

Lines changed: 12 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -3,8 +3,8 @@
33

44
define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
55
; CHECK: VPlan 'Final VPlan for VF={2},UF={1}' {
6-
; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF
7-
; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count
6+
; CHECK-NEXT: Live-in ir<[[VFxUF:.+]]> = VF * UF
7+
; CHECK-NEXT: Live-in ir<[[VTC:%.+]]> = vector-trip-count
88
; CHECK-NEXT: vp<[[TC:%.+]]> = original trip-count
99
; CHECK-EMPTY:
1010
; CHECK-NEXT: ir-bb<entry>:
@@ -16,7 +16,7 @@ define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
1616
; CHECK-EMPTY:
1717
; CHECK-NEXT: <x1> vector loop: {
1818
; CHECK-NEXT: vector.body:
19-
; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
19+
; CHECK-NEXT: SCALAR-PHI vp<[[CAN_IV:%.+]]> = phi ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
2020
; CHECK-NEXT: vp<[[STEPS:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
2121
; CHECK-NEXT: EMIT vp<[[PTR:%.+]]> = ptradd ir<%start>, vp<[[STEPS]]>
2222
; CHECK-NEXT: vp<[[WIDE_PTR:%.+]]> = vector-pointer vp<[[PTR]]>
@@ -76,22 +76,23 @@ define void @switch4_default_common_dest_with_case(ptr %start, ptr %end) {
7676
; CHECK-NEXT: Successor(s): default.2
7777
; CHECK-EMPTY:
7878
; CHECK-NEXT: default.2:
79-
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, vp<[[VFxUF]]>
80-
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, vp<[[VTC]]>
79+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV]]>, ir<[[VFxUF]]>
80+
; CHECK-NEXT: EMIT branch-on-count vp<[[CAN_IV_NEXT]]>, ir<[[VTC]]>
8181
; CHECK-NEXT: No successors
8282
; CHECK-NEXT: }
83-
; CHECK-NEXT: Successor(s): middle.block
83+
; CHECK-NEXT: Successor(s): ir-bb<middle.block>
8484
; CHECK-EMPTY:
85-
; CHECK-NEXT: middle.block:
86-
; CHECK-NEXT: EMIT vp<[[MIDDLE_CMP:%.+]]> = icmp eq vp<[[TC]]>, vp<[[VTC]]>
85+
; CHECK-NEXT: ir-bb<middle.block>:
86+
; CHECK-NEXT: EMIT vp<[[MIDDLE_CMP:%.+]]> = icmp eq vp<[[TC]]>, ir<[[VTC]]>
8787
; CHECK-NEXT: EMIT branch-on-cond vp<[[MIDDLE_CMP]]>
88-
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
88+
; CHECK-NEXT: Successor(s): ir-bb<exit>, ir-bb<scalar.ph>
8989
; CHECK-EMPTY:
90-
; CHECK-NEXT: scalar.ph:
90+
; CHECK-NEXT: ir-bb<scalar.ph>:
91+
; CHECK-NEXT: EMIT vp<[[RESUME:%.+]]> = resume-phi ir<%ind.end>, ir<%start>
9192
; CHECK-NEXT: Successor(s): ir-bb<loop.header>
9293
; CHECK-EMPTY:
9394
; CHECK-NEXT: ir-bb<loop.header>:
94-
; CHECK-NEXT: IR %ptr.iv = phi ptr [ %start, %entry ], [ %ptr.iv.next, %loop.latch ]
95+
; CHECK-NEXT: IR %ptr.iv = phi ptr [ %start, %scalar.ph ], [ %ptr.iv.next, %loop.latch ] (extra operand: vp<[[RESUME]]> from ir-bb<scalar.ph>)
9596
; CHECK-NEXT: IR %l = load i8, ptr %ptr.iv, align 1
9697
; CHECK-NEXT: No successors
9798
; CHECK-EMPTY:

‎llvm/test/Transforms/LoopVectorize/vplan-printing-before-execute.ll

Lines changed: 13 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -57,8 +57,8 @@ define void @test_tc_less_than_16(ptr %A, i64 %N) {
5757
;
5858
; CHECK: Executing best plan with VF=8, UF=2
5959
; CHECK-NEXT: VPlan 'Final VPlan for VF={8},UF={2}' {
60-
; CHECK-NEXT: Live-in vp<[[VFxUF:%.+]]> = VF * UF
61-
; CHECK-NEXT: Live-in vp<[[VTC:%.+]]> = vector-trip-count
60+
; CHECK-NEXT: Live-in ir<[[VFxUF:.+]]> = VF * UF
61+
; CHECK-NEXT: Live-in ir<[[VTC:%.+]]> = vector-trip-count
6262
; CHECK-NEXT: vp<[[TC:%.+]]> = original trip-count
6363
; CHECK-EMPTY:
6464
; CHECK-NEXT: ir-bb<entry>:
@@ -71,7 +71,7 @@ define void @test_tc_less_than_16(ptr %A, i64 %N) {
7171
; CHECK-EMPTY:
7272
; CHECK-NEXT: <x1> vector loop: {
7373
; CHECK-NEXT: vector.body:
74-
; CHECK-NEXT: EMIT vp<[[CAN_IV:%.+]]> = CANONICAL-INDUCTION ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
74+
; CHECK-NEXT: SCALAR-PHI vp<[[CAN_IV:%.+]]> = phi ir<0>, vp<[[CAN_IV_NEXT:%.+]]>
7575
; CHECK-NEXT: vp<[[STEPS1:%.+]]> = SCALAR-STEPS vp<[[CAN_IV]]>, ir<1>
7676
; CHECK-NEXT: EMIT vp<[[PADD1:%.+]]> = ptradd ir<%A>, vp<[[STEPS1]]>
7777
; CHECK-NEXT: vp<[[VPTR1:%.]]> = vector-pointer vp<[[PADD1]]>
@@ -84,23 +84,25 @@ define void @test_tc_less_than_16(ptr %A, i64 %N) {
8484
; CHECK-NEXT: vp<[[VPTR4:%.+]]> = vector-pointer vp<[[PADD1]]>, ir<1>
8585
; CHECK-NEXT: WIDEN store vp<[[VPTR3]]>, ir<%add>
8686
; CHECK-NEXT: WIDEN store vp<[[VPTR4]]>, ir<%add>.1
87-
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV:%.+]]>, vp<[[VFxUF]]>
87+
; CHECK-NEXT: EMIT vp<[[CAN_IV_NEXT]]> = add nuw vp<[[CAN_IV:%.+]]>, ir<[[VFxUF]]>
8888
; CHECK-NEXT: EMIT branch-on-cond ir<true>
8989
; CHECK-NEXT: No successors
9090
; CHECK-NEXT: }
91-
; CHECK-NEXT: Successor(s): middle.block
91+
; CHECK-NEXT: Successor(s): ir-bb<middle.block>
9292
; CHECK-EMPTY:
93-
; CHECK-NEXT: middle.block:
94-
; CHECK-NEXT: EMIT vp<[[C:%.+]]> = icmp eq vp<[[TC]]>, vp<[[VTC]]>
93+
; CHECK-NEXT: ir-bb<middle.block>:
94+
; CHECK-NEXT: EMIT vp<[[C:%.+]]> = icmp eq vp<[[TC]]>, ir<[[VTC]]>
9595
; CHECK-NEXT: EMIT branch-on-cond vp<[[C]]>
96-
; CHECK-NEXT: Successor(s): ir-bb<exit>, scalar.ph
96+
; CHECK-NEXT: Successor(s): ir-bb<exit>, ir-bb<scalar.ph>
9797
; CHECK-EMPTY:
98-
; CHECK-NEXT: scalar.ph:
98+
; CHECK-NEXT: ir-bb<scalar.ph>:
99+
; CHECK-NEXT: EMIT vp<[[RESUME1:%.+]]> = resume-phi ir<%ind.end>, ir<%and>
100+
; CHECK-NEXT: EMIT vp<[[RESUME2:%.+]]>.1 = resume-phi ir<%ind.end1>, ir<%A>
99101
; CHECK-NEXT: Successor(s): ir-bb<loop>
100102
; CHECK-EMPTY:
101103
; CHECK-NEXT: ir-bb<loop>:
102-
; CHECK-NEXT: IR %iv = phi i64 [ %and, %entry ], [ %iv.next, %loop ]
103-
; CHECK-NEXT: IR %p.src = phi ptr [ %A, %entry ], [ %p.src.next, %loop ]
104+
; CHECK-NEXT: IR %iv = phi i64 [ %and, %scalar.ph ], [ %iv.next, %loop ] (extra operand: vp<[[RESUME1]]> from ir-bb<scalar.ph>)
105+
; CHECK-NEXT: IR %p.src = phi ptr [ %A, %scalar.ph ], [ %p.src.next, %loop ] (extra operand: vp<[[RESUME2]]>.1 from ir-bb<scalar.ph>)
104106
; CHECK: IR %cmp = icmp eq i64 %iv.next, 0
105107
; CHECK-NEXT: No successors
106108
; CHECK-EMPTY:

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