x[AArch64][GlobalISel] Enable vector support for G_SELECT->G_FMAXIMUM/MINIMUM.

aemerson · aemerson · commit 07ccf651b95b · 2022-10-03T21:39:52.000+01:00
Vector support seems to work immediately, as long as we run the combine before legalization (so the vector SELECTs don't get lowered) and the legalizer rules are there to enable generation. Differential Revision: https://reviews.llvm.org/D135047
diff --git a/llvm/include/llvm/Target/GlobalISel/Combine.td b/llvm/include/llvm/Target/GlobalISel/Combine.td
@@ -1031,7 +1031,7 @@ def all_combines : GICombineGroup<[trivial_combines, insert_vec_elt_combines,
     form_bitfield_extract, constant_fold, fabs_fneg_fold,
     intdiv_combines, mulh_combines, redundant_neg_operands,
     and_or_disjoint_mask, fma_combines, fold_binop_into_select,
-    sub_add_reg]>;
+    sub_add_reg, select_to_minmax]>;
 
 // A combine group used to for prelegalizer combiners at -O0. The combines in
 // this group have been selected based on experiments to balance code size and
diff --git a/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp b/llvm/lib/CodeGen/GlobalISel/CombinerHelper.cpp
@@ -5985,8 +5985,7 @@ bool CombinerHelper::matchFPSelectToMinMax(Register Dst, Register Cond,
   // And turn it into fminnum/fmaxnum or fmin/fmax based off of the condition.
   LLT DstTy = MRI.getType(Dst);
   // Bail out early on pointers, since we'll never want to fold to a min/max.
-  // TODO: Handle vectors.
-  if (DstTy.isPointer() || DstTy.isVector())
+  if (DstTy.isPointer())
     return false;
   // Match a floating point compare with a less-than/greater-than predicate.
   // TODO: Allow multiple users of the compare if they are all selects.
diff --git a/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp b/llvm/lib/Target/AArch64/GISel/AArch64LegalizerInfo.cpp
@@ -803,10 +803,16 @@ AArch64LegalizerInfo::AArch64LegalizerInfo(const AArch64Subtarget &ST)
       .libcallFor({s128})
       .minScalar(0, MinFPScalar);
 
-  // TODO: Vector types.
   getActionDefinitionsBuilder({G_FMAXIMUM, G_FMINIMUM})
-      .legalFor({MinFPScalar, s32, s64})
-      .minScalar(0, MinFPScalar);
+      .legalFor({MinFPScalar, s32, s64, v2s32, v4s32, v2s64})
+      .legalIf([=](const LegalityQuery &Query) {
+        const auto &Ty = Query.Types[0];
+        return (Ty == v8s16 || Ty == v4s16) && HasFP16;
+      })
+      .minScalar(0, MinFPScalar)
+      .clampNumElements(0, v4s16, v8s16)
+      .clampNumElements(0, v2s32, v4s32)
+      .clampNumElements(0, v2s64, v2s64);
 
   // TODO: Libcall support for s128.
   // TODO: s16 should be legal with full FP16 support.
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaximum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fmaximum.mir
@@ -9,13 +9,17 @@ body:             |
   bb.0:
     liveins: $h0, $h1
     ; FP16-LABEL: name: s16_legal_with_full_fp16
-    ; FP16: %a:_(s16) = COPY $h0
+    ; FP16: liveins: $h0, $h1
+    ; FP16-NEXT: {{  $}}
+    ; FP16-NEXT: %a:_(s16) = COPY $h0
     ; FP16-NEXT: %b:_(s16) = COPY $h1
     ; FP16-NEXT: %legalize_me:_(s16) = G_FMAXIMUM %a, %b
     ; FP16-NEXT: $h0 = COPY %legalize_me(s16)
     ; FP16-NEXT: RET_ReallyLR implicit $h0
     ; NO-FP16-LABEL: name: s16_legal_with_full_fp16
-    ; NO-FP16: %a:_(s16) = COPY $h0
+    ; NO-FP16: liveins: $h0, $h1
+    ; NO-FP16-NEXT: {{  $}}
+    ; NO-FP16-NEXT: %a:_(s16) = COPY $h0
     ; NO-FP16-NEXT: %b:_(s16) = COPY $h1
     ; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %a(s16)
     ; NO-FP16-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %b(s16)
@@ -37,13 +41,17 @@ body:             |
   bb.0:
     liveins: $s0, $s1
     ; FP16-LABEL: name: s32_legal
-    ; FP16: %a:_(s32) = COPY $s0
+    ; FP16: liveins: $s0, $s1
+    ; FP16-NEXT: {{  $}}
+    ; FP16-NEXT: %a:_(s32) = COPY $s0
     ; FP16-NEXT: %b:_(s32) = COPY $s1
     ; FP16-NEXT: %legalize_me:_(s32) = G_FMAXIMUM %a, %b
     ; FP16-NEXT: $s0 = COPY %legalize_me(s32)
     ; FP16-NEXT: RET_ReallyLR implicit $s0
     ; NO-FP16-LABEL: name: s32_legal
-    ; NO-FP16: %a:_(s32) = COPY $s0
+    ; NO-FP16: liveins: $s0, $s1
+    ; NO-FP16-NEXT: {{  $}}
+    ; NO-FP16-NEXT: %a:_(s32) = COPY $s0
     ; NO-FP16-NEXT: %b:_(s32) = COPY $s1
     ; NO-FP16-NEXT: %legalize_me:_(s32) = G_FMAXIMUM %a, %b
     ; NO-FP16-NEXT: $s0 = COPY %legalize_me(s32)
@@ -62,13 +70,17 @@ body:             |
   bb.0:
     liveins: $d0, $d1
     ; FP16-LABEL: name: s64_legal
-    ; FP16: %a:_(s64) = COPY $d0
+    ; FP16: liveins: $d0, $d1
+    ; FP16-NEXT: {{  $}}
+    ; FP16-NEXT: %a:_(s64) = COPY $d0
     ; FP16-NEXT: %b:_(s64) = COPY $d1
     ; FP16-NEXT: %legalize_me:_(s64) = G_FMAXIMUM %a, %b
     ; FP16-NEXT: $d0 = COPY %legalize_me(s64)
     ; FP16-NEXT: RET_ReallyLR implicit $d0
     ; NO-FP16-LABEL: name: s64_legal
-    ; NO-FP16: %a:_(s64) = COPY $d0
+    ; NO-FP16: liveins: $d0, $d1
+    ; NO-FP16-NEXT: {{  $}}
+    ; NO-FP16-NEXT: %a:_(s64) = COPY $d0
     ; NO-FP16-NEXT: %b:_(s64) = COPY $d1
     ; NO-FP16-NEXT: %legalize_me:_(s64) = G_FMAXIMUM %a, %b
     ; NO-FP16-NEXT: $d0 = COPY %legalize_me(s64)
@@ -78,3 +90,62 @@ body:             |
     %legalize_me:_(s64) = G_FMAXIMUM %a, %b
     $d0 = COPY %legalize_me(s64)
     RET_ReallyLR implicit $d0
+...
+---
+name:            v2s32
+alignment:       4
+body:             |
+  bb.0:
+    liveins: $d0, $d1
+    ; FP16-LABEL: name: v2s32
+    ; FP16: liveins: $d0, $d1
+    ; FP16-NEXT: {{  $}}
+    ; FP16-NEXT: %a:_(<2 x s32>) = COPY $d0
+    ; FP16-NEXT: %b:_(<2 x s32>) = COPY $d1
+    ; FP16-NEXT: %maximum:_(<2 x s32>) = G_FMAXIMUM %a, %b
+    ; FP16-NEXT: $d0 = COPY %maximum(<2 x s32>)
+    ; FP16-NEXT: RET_ReallyLR implicit $d0
+    ; NO-FP16-LABEL: name: v2s32
+    ; NO-FP16: liveins: $d0, $d1
+    ; NO-FP16-NEXT: {{  $}}
+    ; NO-FP16-NEXT: %a:_(<2 x s32>) = COPY $d0
+    ; NO-FP16-NEXT: %b:_(<2 x s32>) = COPY $d1
+    ; NO-FP16-NEXT: %maximum:_(<2 x s32>) = G_FMAXIMUM %a, %b
+    ; NO-FP16-NEXT: $d0 = COPY %maximum(<2 x s32>)
+    ; NO-FP16-NEXT: RET_ReallyLR implicit $d0
+    %a:_(<2 x s32>) = COPY $d0
+    %b:_(<2 x s32>) = COPY $d1
+    %maximum:_(<2 x s32>) = G_FMAXIMUM %a, %b
+    $d0 = COPY %maximum(<2 x s32>)
+    RET_ReallyLR implicit $d0
+
+...
+---
+name:            v4s32
+alignment:       4
+body:             |
+  bb.0:
+    liveins: $q0, $q1
+    ; FP16-LABEL: name: v4s32
+    ; FP16: liveins: $q0, $q1
+    ; FP16-NEXT: {{  $}}
+    ; FP16-NEXT: %a:_(<4 x s32>) = COPY $q0
+    ; FP16-NEXT: %b:_(<4 x s32>) = COPY $q1
+    ; FP16-NEXT: %maximum:_(<4 x s32>) = G_FMAXIMUM %a, %b
+    ; FP16-NEXT: $q0 = COPY %maximum(<4 x s32>)
+    ; FP16-NEXT: RET_ReallyLR implicit $q0
+    ; NO-FP16-LABEL: name: v4s32
+    ; NO-FP16: liveins: $q0, $q1
+    ; NO-FP16-NEXT: {{  $}}
+    ; NO-FP16-NEXT: %a:_(<4 x s32>) = COPY $q0
+    ; NO-FP16-NEXT: %b:_(<4 x s32>) = COPY $q1
+    ; NO-FP16-NEXT: %maximum:_(<4 x s32>) = G_FMAXIMUM %a, %b
+    ; NO-FP16-NEXT: $q0 = COPY %maximum(<4 x s32>)
+    ; NO-FP16-NEXT: RET_ReallyLR implicit $q0
+    %a:_(<4 x s32>) = COPY $q0
+    %b:_(<4 x s32>) = COPY $q1
+    %maximum:_(<4 x s32>) = G_FMAXIMUM %a, %b
+    $q0 = COPY %maximum(<4 x s32>)
+    RET_ReallyLR implicit $q0
+
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminimum.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalize-fminimum.mir
@@ -9,13 +9,17 @@ body:             |
   bb.0:
     liveins: $h0, $h1
     ; FP16-LABEL: name: s16_legal_with_full_fp16
-    ; FP16: %a:_(s16) = COPY $h0
+    ; FP16: liveins: $h0, $h1
+    ; FP16-NEXT: {{  $}}
+    ; FP16-NEXT: %a:_(s16) = COPY $h0
     ; FP16-NEXT: %b:_(s16) = COPY $h1
     ; FP16-NEXT: %legalize_me:_(s16) = G_FMINIMUM %a, %b
     ; FP16-NEXT: $h0 = COPY %legalize_me(s16)
     ; FP16-NEXT: RET_ReallyLR implicit $h0
     ; NO-FP16-LABEL: name: s16_legal_with_full_fp16
-    ; NO-FP16: %a:_(s16) = COPY $h0
+    ; NO-FP16: liveins: $h0, $h1
+    ; NO-FP16-NEXT: {{  $}}
+    ; NO-FP16-NEXT: %a:_(s16) = COPY $h0
     ; NO-FP16-NEXT: %b:_(s16) = COPY $h1
     ; NO-FP16-NEXT: [[FPEXT:%[0-9]+]]:_(s32) = G_FPEXT %a(s16)
     ; NO-FP16-NEXT: [[FPEXT1:%[0-9]+]]:_(s32) = G_FPEXT %b(s16)
@@ -37,13 +41,17 @@ body:             |
   bb.0:
     liveins: $s0, $s1
     ; FP16-LABEL: name: s32_legal
-    ; FP16: %a:_(s32) = COPY $s0
+    ; FP16: liveins: $s0, $s1
+    ; FP16-NEXT: {{  $}}
+    ; FP16-NEXT: %a:_(s32) = COPY $s0
     ; FP16-NEXT: %b:_(s32) = COPY $s1
     ; FP16-NEXT: %legalize_me:_(s32) = G_FMINIMUM %a, %b
     ; FP16-NEXT: $s0 = COPY %legalize_me(s32)
     ; FP16-NEXT: RET_ReallyLR implicit $s0
     ; NO-FP16-LABEL: name: s32_legal
-    ; NO-FP16: %a:_(s32) = COPY $s0
+    ; NO-FP16: liveins: $s0, $s1
+    ; NO-FP16-NEXT: {{  $}}
+    ; NO-FP16-NEXT: %a:_(s32) = COPY $s0
     ; NO-FP16-NEXT: %b:_(s32) = COPY $s1
     ; NO-FP16-NEXT: %legalize_me:_(s32) = G_FMINIMUM %a, %b
     ; NO-FP16-NEXT: $s0 = COPY %legalize_me(s32)
@@ -62,13 +70,17 @@ body:             |
   bb.0:
     liveins: $d0, $d1
     ; FP16-LABEL: name: s64_legal
-    ; FP16: %a:_(s64) = COPY $d0
+    ; FP16: liveins: $d0, $d1
+    ; FP16-NEXT: {{  $}}
+    ; FP16-NEXT: %a:_(s64) = COPY $d0
     ; FP16-NEXT: %b:_(s64) = COPY $d1
     ; FP16-NEXT: %legalize_me:_(s64) = G_FMINIMUM %a, %b
     ; FP16-NEXT: $d0 = COPY %legalize_me(s64)
     ; FP16-NEXT: RET_ReallyLR implicit $d0
     ; NO-FP16-LABEL: name: s64_legal
-    ; NO-FP16: %a:_(s64) = COPY $d0
+    ; NO-FP16: liveins: $d0, $d1
+    ; NO-FP16-NEXT: {{  $}}
+    ; NO-FP16-NEXT: %a:_(s64) = COPY $d0
     ; NO-FP16-NEXT: %b:_(s64) = COPY $d1
     ; NO-FP16-NEXT: %legalize_me:_(s64) = G_FMINIMUM %a, %b
     ; NO-FP16-NEXT: $d0 = COPY %legalize_me(s64)
@@ -78,3 +90,77 @@ body:             |
     %legalize_me:_(s64) = G_FMINIMUM %a, %b
     $d0 = COPY %legalize_me(s64)
     RET_ReallyLR implicit $d0
+...
+---
+name:            v4s32
+alignment:       4
+body:             |
+  bb.0:
+    liveins: $q0, $q1
+    ; FP16-LABEL: name: v4s32
+    ; FP16: liveins: $q0, $q1
+    ; FP16-NEXT: {{  $}}
+    ; FP16-NEXT: %a:_(<4 x s32>) = COPY $q0
+    ; FP16-NEXT: %b:_(<4 x s32>) = COPY $q1
+    ; FP16-NEXT: %minimum:_(<4 x s32>) = G_FMINIMUM %a, %b
+    ; FP16-NEXT: $q0 = COPY %minimum(<4 x s32>)
+    ; FP16-NEXT: RET_ReallyLR implicit $q0
+    ; NO-FP16-LABEL: name: v4s32
+    ; NO-FP16: liveins: $q0, $q1
+    ; NO-FP16-NEXT: {{  $}}
+    ; NO-FP16-NEXT: %a:_(<4 x s32>) = COPY $q0
+    ; NO-FP16-NEXT: %b:_(<4 x s32>) = COPY $q1
+    ; NO-FP16-NEXT: %minimum:_(<4 x s32>) = G_FMINIMUM %a, %b
+    ; NO-FP16-NEXT: $q0 = COPY %minimum(<4 x s32>)
+    ; NO-FP16-NEXT: RET_ReallyLR implicit $q0
+    %a:_(<4 x s32>) = COPY $q0
+    %b:_(<4 x s32>) = COPY $q1
+    %minimum:_(<4 x s32>) = G_FMINIMUM %a, %b
+    $q0 = COPY %minimum(<4 x s32>)
+    RET_ReallyLR implicit $q0
+
+...
+
+---
+name:            v8s32
+alignment:       4
+body:             |
+  bb.0:
+    liveins: $q0, $q1, $q2, $q3
+    ; FP16-LABEL: name: v8s32
+    ; FP16: liveins: $q0, $q1, $q2, $q3
+    ; FP16-NEXT: {{  $}}
+    ; FP16-NEXT: %a:_(<4 x s32>) = COPY $q0
+    ; FP16-NEXT: %b:_(<4 x s32>) = COPY $q1
+    ; FP16-NEXT: %c:_(<4 x s32>) = COPY $q2
+    ; FP16-NEXT: %d:_(<4 x s32>) = COPY $q3
+    ; FP16-NEXT: [[FMINIMUM:%[0-9]+]]:_(<4 x s32>) = G_FMINIMUM %a, %c
+    ; FP16-NEXT: [[FMINIMUM1:%[0-9]+]]:_(<4 x s32>) = G_FMINIMUM %b, %d
+    ; FP16-NEXT: $q0 = COPY [[FMINIMUM]](<4 x s32>)
+    ; FP16-NEXT: $q1 = COPY [[FMINIMUM1]](<4 x s32>)
+    ; FP16-NEXT: RET_ReallyLR implicit $q0
+    ; NO-FP16-LABEL: name: v8s32
+    ; NO-FP16: liveins: $q0, $q1, $q2, $q3
+    ; NO-FP16-NEXT: {{  $}}
+    ; NO-FP16-NEXT: %a:_(<4 x s32>) = COPY $q0
+    ; NO-FP16-NEXT: %b:_(<4 x s32>) = COPY $q1
+    ; NO-FP16-NEXT: %c:_(<4 x s32>) = COPY $q2
+    ; NO-FP16-NEXT: %d:_(<4 x s32>) = COPY $q3
+    ; NO-FP16-NEXT: [[FMINIMUM:%[0-9]+]]:_(<4 x s32>) = G_FMINIMUM %a, %c
+    ; NO-FP16-NEXT: [[FMINIMUM1:%[0-9]+]]:_(<4 x s32>) = G_FMINIMUM %b, %d
+    ; NO-FP16-NEXT: $q0 = COPY [[FMINIMUM]](<4 x s32>)
+    ; NO-FP16-NEXT: $q1 = COPY [[FMINIMUM1]](<4 x s32>)
+    ; NO-FP16-NEXT: RET_ReallyLR implicit $q0
+    %a:_(<4 x s32>) = COPY $q0
+    %b:_(<4 x s32>) = COPY $q1
+    %c:_(<4 x s32>) = COPY $q2
+    %d:_(<4 x s32>) = COPY $q3
+    %v1:_(<8 x s32>) = G_CONCAT_VECTORS %a, %b
+    %v2:_(<8 x s32>) = G_CONCAT_VECTORS %c, %d
+    %minimum:_(<8 x s32>) = G_FMINIMUM %v1, %v2
+    %uv1:_(<4 x s32>), %uv2:_(<4 x s32>) = G_UNMERGE_VALUES %minimum
+    $q0 = COPY %uv1(<4 x s32>)
+    $q1 = COPY %uv2(<4 x s32>)
+    RET_ReallyLR implicit $q0
+
+...
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir b/llvm/test/CodeGen/AArch64/GlobalISel/legalizer-info-validation.mir
@@ -510,11 +510,11 @@
 # DEBUG-NEXT: .. imm index coverage check SKIPPED: no rules defined
 # DEBUG-NEXT: G_FMINIMUM (opcode {{[0-9]+}}): 1 type index
 # DEBUG-NEXT: .. opcode {{[0-9]+}} is aliased to {{[0-9]+}}
-# DEBUG-NEXT: .. the first uncovered type index: 1, OK
-# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: G_FMAXIMUM (opcode {{[0-9]+}}): 1 type index
-# DEBUG-NEXT: .. the first uncovered type index: 1, OK
-# DEBUG-NEXT: .. the first uncovered imm index: 0, OK
+# DEBUG-NEXT: .. type index coverage check SKIPPED: user-defined predicate detected
+# DEBUG-NEXT: .. imm index coverage check SKIPPED: user-defined predicate detected
 # DEBUG-NEXT: G_PTR_ADD (opcode {{[0-9]+}}): 2 type indices, 0 imm indices
 # DEBUG-NEXT: .. the first uncovered type index: 2, OK
 # DEBUG-NEXT: .. the first uncovered imm index: 0, OK
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir b/llvm/test/CodeGen/AArch64/GlobalISel/prelegalizer-combiner-select-to-fminmax.mir
diff --git a/llvm/test/CodeGen/AArch64/GlobalISel/select-to-fmin-fmax.ll b/llvm/test/CodeGen/AArch64/GlobalISel/select-to-fmin-fmax.ll
