Skip to content

Commit 06d10d4

Browse files
authored
[RISCV] Make Zcmt imply Zicsr. (llvm#75464)
This patch fixes build attributes w/r to Zcmt extension dependency on Zicsr.
1 parent a756dc4 commit 06d10d4

File tree

3 files changed

+6
-4
lines changed

3 files changed

+6
-4
lines changed

llvm/lib/Support/RISCVISAInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1007,7 +1007,7 @@ static const char *ImpliedExtsZcd[] = {"d", "zca"};
10071007
static const char *ImpliedExtsZce[] = {"zcb", "zcmp", "zcmt"};
10081008
static const char *ImpliedExtsZcf[] = {"f", "zca"};
10091009
static const char *ImpliedExtsZcmp[] = {"zca"};
1010-
static const char *ImpliedExtsZcmt[] = {"zca"};
1010+
static const char *ImpliedExtsZcmt[] = {"zca", "zicsr"};
10111011
static const char *ImpliedExtsZdinx[] = {"zfinx"};
10121012
static const char *ImpliedExtsZfa[] = {"f"};
10131013
static const char *ImpliedExtsZfbfmin[] = {"f"};

llvm/test/MC/RISCV/attribute-arch.s

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -244,7 +244,7 @@
244244
# CHECK: attribute 5, "rv32i2p1_zca1p0_zcmp1p0"
245245

246246
.attribute arch, "rv32izcmt1p0"
247-
# CHECK: attribute 5, "rv32i2p1_zca1p0_zcmt1p0"
247+
# CHECK: attribute 5, "rv32i2p1_zicsr2p0_zca1p0_zcmt1p0"
248248

249249
.attribute arch, "rv64i_xsfvcp"
250250
# CHECK: attribute 5, "rv64i2p1_zicsr2p0_zve32x1p0_zvl32b1p0_xsfvcp1p0"

llvm/unittests/Support/RISCVISAInfoTest.cpp

Lines changed: 4 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -519,8 +519,9 @@ TEST(ParseArchString, ZceImplication) {
519519
ASSERT_THAT_EXPECTED(MaybeRV32IZce, Succeeded());
520520
RISCVISAInfo::OrderedExtensionMap ExtsRV32IZce =
521521
(*MaybeRV32IZce)->getExtensions();
522-
EXPECT_EQ(ExtsRV32IZce.size(), 6UL);
522+
EXPECT_EQ(ExtsRV32IZce.size(), 7UL);
523523
EXPECT_EQ(ExtsRV32IZce.count("i"), 1U);
524+
EXPECT_EQ(ExtsRV32IZce.count("zicsr"), 1U);
524525
EXPECT_EQ(ExtsRV32IZce.count("zca"), 1U);
525526
EXPECT_EQ(ExtsRV32IZce.count("zcb"), 1U);
526527
EXPECT_EQ(ExtsRV32IZce.count("zce"), 1U);
@@ -562,8 +563,9 @@ TEST(ParseArchString, ZceImplication) {
562563
ASSERT_THAT_EXPECTED(MaybeRV64IZce, Succeeded());
563564
RISCVISAInfo::OrderedExtensionMap ExtsRV64IZce =
564565
(*MaybeRV64IZce)->getExtensions();
565-
EXPECT_EQ(ExtsRV64IZce.size(), 6UL);
566+
EXPECT_EQ(ExtsRV64IZce.size(), 7UL);
566567
EXPECT_EQ(ExtsRV64IZce.count("i"), 1U);
568+
EXPECT_EQ(ExtsRV64IZce.count("zicsr"), 1U);
567569
EXPECT_EQ(ExtsRV64IZce.count("zca"), 1U);
568570
EXPECT_EQ(ExtsRV64IZce.count("zcb"), 1U);
569571
EXPECT_EQ(ExtsRV64IZce.count("zce"), 1U);

0 commit comments

Comments
 (0)