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1 | 1 | //! Compiler intrinsics.
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2 | 2 | //!
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3 |
| -//! The corresponding definitions are in <https://github.com/rust-lang/rust/blob/master/compiler/rustc_codegen_llvm/src/intrinsic.rs>. |
4 |
| -//! The corresponding const implementations are in <https://github.com/rust-lang/rust/blob/master/compiler/rustc_const_eval/src/interpret/intrinsics.rs>. |
| 3 | +//! These are the imports making intrinsics available to Rust code. The actual implementations live in the compiler. |
| 4 | +//! Some of these intrinsics are lowered to MIR in <https://github.com/rust-lang/rust/blob/master/compiler/rustc_mir_transform/src/lower_intrinsics.rs>. |
| 5 | +//! The remaining intrinsics are implemented for the LLVM backend in <https://github.com/rust-lang/rust/blob/master/compiler/rustc_codegen_ssa/src/mir/intrinsic.rs> |
| 6 | +//! and <https://github.com/rust-lang/rust/blob/master/compiler/rustc_codegen_llvm/src/intrinsic.rs>, |
| 7 | +//! and for const evaluation in <https://github.com/rust-lang/rust/blob/master/compiler/rustc_const_eval/src/interpret/intrinsics.rs>. |
5 | 8 | //!
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6 | 9 | //! # Const intrinsics
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7 | 10 | //!
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20 | 23 | //!
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21 | 24 | //! The volatile intrinsics provide operations intended to act on I/O
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22 | 25 | //! memory, which are guaranteed to not be reordered by the compiler
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23 |
| -//! across other volatile intrinsics. See the LLVM documentation on |
24 |
| -//! [[volatile]]. |
25 |
| -//! |
26 |
| -//! [volatile]: https://llvm.org/docs/LangRef.html#volatile-memory-accesses |
| 26 | +//! across other volatile intrinsics. See [`read_volatile`][ptr::read_volatile] |
| 27 | +//! and [`write_volatile`][ptr::write_volatile]. |
27 | 28 | //!
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28 | 29 | //! # Atomics
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29 | 30 | //!
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30 | 31 | //! The atomic intrinsics provide common atomic operations on machine
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31 |
| -//! words, with multiple possible memory orderings. They obey the same |
32 |
| -//! semantics as C++11. See the LLVM documentation on [[atomics]]. |
33 |
| -//! |
34 |
| -//! [atomics]: https://llvm.org/docs/Atomics.html |
35 |
| -//! |
36 |
| -//! A quick refresher on memory ordering: |
37 |
| -//! |
38 |
| -//! * Acquire - a barrier for acquiring a lock. Subsequent reads and writes |
39 |
| -//! take place after the barrier. |
40 |
| -//! * Release - a barrier for releasing a lock. Preceding reads and writes |
41 |
| -//! take place before the barrier. |
42 |
| -//! * Sequentially consistent - sequentially consistent operations are |
43 |
| -//! guaranteed to happen in order. This is the standard mode for working |
44 |
| -//! with atomic types and is equivalent to Java's `volatile`. |
| 32 | +//! words, with multiple possible memory orderings. See the |
| 33 | +//! [atomic types][crate::sync::atomic] docs for details. |
45 | 34 | //!
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46 | 35 | //! # Unwinding
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47 | 36 | //!
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