We read every piece of feedback, and take your input very seriously.
To see all available qualifiers, see our documentation.
There was an error while loading. Please reload this page.
1 parent 08cc09e commit 2d39911Copy full SHA for 2d39911
cores/esp8266/core_esp8266_features.h
@@ -50,6 +50,7 @@
50
// level 15 will disable ALL interrupts,
51
// level 0 will enable ALL interrupts,
52
//
53
+#ifndef CORE_MOCK
54
#define xt_rsil(level) (__extension__({uint32_t state; __asm__ __volatile__("rsil %0," __STRINGIFY(level) : "=a" (state) :: "memory"); state;}))
55
#define xt_wsr_ps(state) __asm__ __volatile__("wsr %0,ps; isync" :: "a" (state) : "memory")
56
@@ -58,5 +59,6 @@ inline uint32_t esp_get_cycle_count() {
58
59
__asm__ __volatile__("rsr %0,ccount":"=a"(ccount));
60
return ccount;
61
}
62
+#endif // not CORE_MOCK
63
64
#endif
0 commit comments