|
1 | 1 | import machine
|
2 | 2 |
|
3 | 3 |
|
4 |
| -class I2CBus(object): |
| 4 | +class I2C(object): |
| 5 | + class Bus(object): |
| 6 | + |
| 7 | + def __init__(self, host, scl, sda, freq=400000, use_locks=False): |
| 8 | + self._bus = machine.I2C( |
| 9 | + host, |
| 10 | + scl=machine.Pin(scl), |
| 11 | + sda=machine.Pin(sda), |
| 12 | + freq=freq |
| 13 | + ) |
5 | 14 |
|
6 |
| - def __init__(self, scl, sda, freq=400000, host=None, use_locks=False): |
7 |
| - if host is None: |
8 |
| - if (scl, sda) == (19, 18): |
9 |
| - host = 0 |
| 15 | + if use_locks: |
| 16 | + import _thread |
| 17 | + self._lock = _thread.allocate_lock() |
10 | 18 | else:
|
11 |
| - host = 1 |
12 |
| - |
13 |
| - self._bus = machine.I2C( |
14 |
| - host, |
15 |
| - scl=machine.Pin(scl), |
16 |
| - sda=machine.Pin(sda), |
17 |
| - freq=freq |
18 |
| - ) |
19 |
| - |
20 |
| - if use_locks: |
21 |
| - import _thread |
22 |
| - self._lock = _thread.allocate_lock() |
23 |
| - else: |
24 |
| - class Lock(object): |
| 19 | + class Lock(object): |
25 | 20 |
|
26 |
| - def acquire(self): |
27 |
| - pass |
| 21 | + def acquire(self): |
| 22 | + pass |
28 | 23 |
|
29 |
| - def release(self): |
30 |
| - pass |
| 24 | + def release(self): |
| 25 | + pass |
31 | 26 |
|
32 |
| - def is_locked(self): |
33 |
| - return False |
| 27 | + def is_locked(self): |
| 28 | + return False |
34 | 29 |
|
35 |
| - self._lock = Lock() |
| 30 | + self._lock = Lock() |
36 | 31 |
|
37 |
| - def __enter__(self): |
38 |
| - self._lock.acquire() |
39 |
| - return self |
| 32 | + def __enter__(self): |
| 33 | + self._lock.acquire() |
| 34 | + return self |
40 | 35 |
|
41 |
| - def __exit__(self, exc_type, exc_val, exc_tb): |
42 |
| - self._lock.release() |
| 36 | + def __exit__(self, exc_type, exc_val, exc_tb): |
| 37 | + self._lock.release() |
43 | 38 |
|
44 |
| - def scan(self): |
45 |
| - self._lock.acquire() |
46 |
| - data = self._bus.scan() |
47 |
| - self._lock.release() |
48 |
| - return data |
| 39 | + def scan(self): |
| 40 | + self._lock.acquire() |
| 41 | + data = self._bus.scan() |
| 42 | + self._lock.release() |
| 43 | + return data |
49 | 44 |
|
50 |
| - def start(self): |
51 |
| - self._bus.start() |
| 45 | + def start(self): |
| 46 | + self._bus.start() |
52 | 47 |
|
53 |
| - def stop(self): |
54 |
| - self._bus.stop() |
| 48 | + def stop(self): |
| 49 | + self._bus.stop() |
55 | 50 |
|
56 |
| - def readinto(self, buf, nack=True): |
57 |
| - self._bus.readinto(buf, nack) |
| 51 | + def readinto(self, buf, nack=True): |
| 52 | + self._bus.readinto(buf, nack) |
58 | 53 |
|
59 |
| - def write(self, buf): |
60 |
| - self._bus.write(buf) |
| 54 | + def write(self, buf): |
| 55 | + self._bus.write(buf) |
61 | 56 |
|
62 |
| - def readfrom(self, addr, nbytes, stop=True): |
63 |
| - return self._bus.readfrom(addr, nbytes, stop) |
| 57 | + def readfrom(self, addr, nbytes, stop=True): |
| 58 | + return self._bus.readfrom(addr, nbytes, stop) |
64 | 59 |
|
65 |
| - def readfrom_into(self, addr, buf, stop=True): |
66 |
| - self._bus.readfrom_into(addr, buf, stop) |
| 60 | + def readfrom_into(self, addr, buf, stop=True): |
| 61 | + self._bus.readfrom_into(addr, buf, stop) |
67 | 62 |
|
68 |
| - def writeto(self, addr, buf, stop=True): |
69 |
| - self._bus.writeto(addr, buf, stop) |
| 63 | + def writeto(self, addr, buf, stop=True): |
| 64 | + self._bus.writeto(addr, buf, stop) |
70 | 65 |
|
71 |
| - def writevto(self, addr, vector, stop=True): |
72 |
| - self._bus.writevto(addr, vector, stop) |
| 66 | + def writevto(self, addr, vector, stop=True): |
| 67 | + self._bus.writevto(addr, vector, stop) |
73 | 68 |
|
74 |
| - def readfrom_mem(self, addr, memaddr, nbytes, addrsize=8): |
75 |
| - return self._bus.readfrom_mem(addr, memaddr, nbytes, addrsize=addrsize) |
| 69 | + def readfrom_mem(self, addr, memaddr, nbytes, addrsize=8): |
| 70 | + return self._bus.readfrom_mem(addr, memaddr, nbytes, addrsize=addrsize) |
76 | 71 |
|
77 |
| - def readfrom_mem_into(self, addr, memaddr, buf, addrsize=8): |
78 |
| - self._bus.readfrom_mem_into(addr, memaddr, buf, addrsize=addrsize) |
| 72 | + def readfrom_mem_into(self, addr, memaddr, buf, addrsize=8): |
| 73 | + self._bus.readfrom_mem_into(addr, memaddr, buf, addrsize=addrsize) |
79 | 74 |
|
80 |
| - def writeto_mem(self, addr, memaddr, buf, addrsize=8): |
81 |
| - self._bus.writeto_mem(addr, memaddr, buf, addrsize=addrsize) |
| 75 | + def writeto_mem(self, addr, memaddr, buf, addrsize=8): |
| 76 | + self._bus.writeto_mem(addr, memaddr, buf, addrsize=addrsize) |
82 | 77 |
|
83 |
| - def add_device(self, dev_id, reg_bits=8): |
84 |
| - return I2CDevice(self, dev_id, reg_bits) |
| 78 | + class Device(object): |
85 | 79 |
|
| 80 | + def __init__(self, bus, dev_id, reg_bits=8): |
| 81 | + self._bus = bus |
| 82 | + self.dev_id = dev_id |
| 83 | + self._reg_bits = reg_bits |
86 | 84 |
|
87 |
| -class I2CDevice(object): |
| 85 | + def write_readinto(self, write_buf, read_buf): |
| 86 | + memaddr = 0 |
| 87 | + for i in range(int(self._reg_bits / 8)): |
| 88 | + memaddr |= write_buf[i] << i |
| 89 | + self.read_mem(memaddr, buf=read_buf) |
88 | 90 |
|
89 |
| - def __init__(self, bus, dev_id, reg_bits=8): |
90 |
| - self._bus = bus |
91 |
| - self.dev_id = dev_id |
92 |
| - self._reg_bits = reg_bits |
| 91 | + def read_mem(self, memaddr, num_bytes=None, buf=None): |
| 92 | + with self._bus: |
| 93 | + if num_bytes is not None: |
| 94 | + return self._bus.readfrom_mem( |
| 95 | + self.dev_id, |
| 96 | + memaddr, |
| 97 | + num_bytes, |
| 98 | + addrsize=self._reg_bits |
| 99 | + ) |
| 100 | + else: |
| 101 | + self._bus.readfrom_mem_into( |
| 102 | + self.dev_id, |
| 103 | + memaddr, |
| 104 | + buf, |
| 105 | + addrsize=self._reg_bits |
| 106 | + ) |
| 107 | + return |
93 | 108 |
|
94 |
| - def read_mem(self, memaddr, num_bytes=None, buf=None): |
95 |
| - with self._bus: |
96 |
| - if num_bytes is not None: |
97 |
| - return self._bus.readfrom_mem( |
98 |
| - self.dev_id, |
99 |
| - memaddr, |
100 |
| - num_bytes, |
101 |
| - addrsize=self._reg_bits |
102 |
| - ) |
103 |
| - else: |
104 |
| - self._bus.readfrom_mem_into( |
| 109 | + def write_mem(self, memaddr, buf): |
| 110 | + with self._bus: |
| 111 | + self._bus.writeto_mem( |
105 | 112 | self.dev_id,
|
106 | 113 | memaddr,
|
107 | 114 | buf,
|
108 | 115 | addrsize=self._reg_bits
|
109 | 116 | )
|
110 |
| - return |
111 |
| - |
112 |
| - def write_mem(self, memaddr, buf): |
113 |
| - with self._bus: |
114 |
| - self._bus.writeto_mem( |
115 |
| - self.dev_id, |
116 |
| - memaddr, |
117 |
| - buf, |
118 |
| - addrsize=self._reg_bits |
119 |
| - ) |
120 | 117 |
|
121 |
| - def read(self, num_bytes=None, buf=None): |
122 |
| - with self._bus: |
123 |
| - if num_bytes is not None: |
124 |
| - return self._bus.readfrom(self.dev_id, num_bytes) |
| 118 | + def read(self, num_bytes=None, buf=None): |
| 119 | + with self._bus: |
| 120 | + if num_bytes is not None: |
| 121 | + return self._bus.readfrom(self.dev_id, num_bytes) |
| 122 | + else: |
| 123 | + self._bus.readfrom_into(self.dev_id, buf) |
| 124 | + |
| 125 | + def write(self, buf): |
| 126 | + memaddr = 0 |
| 127 | + for i in range(int(self._reg_bits / 8)): |
| 128 | + memaddr |= buf[i] << i |
125 | 129 | else:
|
126 |
| - self._bus.readfrom_into(self.dev_id, buf) |
| 130 | + i = int(self._reg_bits / 8) - 1 |
127 | 131 |
|
128 |
| - def write(self, buf): |
129 |
| - with self._bus: |
130 |
| - self._bus.writeto(self.dev_id, buf) |
| 132 | + self.write_mem(memaddr, buf=buf[i + 1:]) |
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