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[RISCV] Use PromoteSetCCOperands to promote operands for UMAX/UMIN during type legalization. (#82716)
For RISC-V, we were always choosing to sign extend when promoting i32->i64. If the promoted inputs happen to be zero extended already, we should use zero extend instead. This is what we do for SETCC.
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5 files changed

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Diff for: ‎llvm/lib/CodeGen/SelectionDAG/LegalizeIntegerTypes.cpp

+32-22
Original file line numberDiff line numberDiff line change
@@ -1354,10 +1354,13 @@ SDValue DAGTypeLegalizer::PromoteIntRes_ZExtIntBinOp(SDNode *N) {
13541354
}
13551355

13561356
SDValue DAGTypeLegalizer::PromoteIntRes_UMINUMAX(SDNode *N) {
1357+
SDValue LHS = N->getOperand(0);
1358+
SDValue RHS = N->getOperand(1);
1359+
13571360
// It doesn't matter if we sign extend or zero extend in the inputs. So do
1358-
// whatever is best for the target.
1359-
SDValue LHS = SExtOrZExtPromotedInteger(N->getOperand(0));
1360-
SDValue RHS = SExtOrZExtPromotedInteger(N->getOperand(1));
1361+
// whatever is best for the target and the promoted operands.
1362+
SExtOrZExtPromotedOperands(LHS, RHS);
1363+
13611364
return DAG.getNode(N->getOpcode(), SDLoc(N),
13621365
LHS.getValueType(), LHS, RHS);
13631366
}
@@ -1922,25 +1925,10 @@ bool DAGTypeLegalizer::PromoteIntegerOperand(SDNode *N, unsigned OpNo) {
19221925
return false;
19231926
}
19241927

1925-
/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
1926-
/// shared among BR_CC, SELECT_CC, and SETCC handlers.
1927-
void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &LHS, SDValue &RHS,
1928-
ISD::CondCode CCCode) {
1929-
// We have to insert explicit sign or zero extends. Note that we could
1930-
// insert sign extends for ALL conditions. For those operations where either
1931-
// zero or sign extension would be valid, we ask the target which extension
1932-
// it would prefer.
1933-
1934-
// Signed comparisons always require sign extension.
1935-
if (ISD::isSignedIntSetCC(CCCode)) {
1936-
LHS = SExtPromotedInteger(LHS);
1937-
RHS = SExtPromotedInteger(RHS);
1938-
return;
1939-
}
1940-
1941-
assert((ISD::isUnsignedIntSetCC(CCCode) || ISD::isIntEqualitySetCC(CCCode)) &&
1942-
"Unknown integer comparison!");
1943-
1928+
// These operands can be either sign extended or zero extended as long as we
1929+
// treat them the same. If an extension is free, choose that. Otherwise, follow
1930+
// target preference.
1931+
void DAGTypeLegalizer::SExtOrZExtPromotedOperands(SDValue &LHS, SDValue &RHS) {
19441932
SDValue OpL = GetPromotedInteger(LHS);
19451933
SDValue OpR = GetPromotedInteger(RHS);
19461934

@@ -1984,6 +1972,28 @@ void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &LHS, SDValue &RHS,
19841972
RHS = ZExtPromotedInteger(RHS);
19851973
}
19861974

1975+
/// PromoteSetCCOperands - Promote the operands of a comparison. This code is
1976+
/// shared among BR_CC, SELECT_CC, and SETCC handlers.
1977+
void DAGTypeLegalizer::PromoteSetCCOperands(SDValue &LHS, SDValue &RHS,
1978+
ISD::CondCode CCCode) {
1979+
// We have to insert explicit sign or zero extends. Note that we could
1980+
// insert sign extends for ALL conditions. For those operations where either
1981+
// zero or sign extension would be valid, we ask the target which extension
1982+
// it would prefer.
1983+
1984+
// Signed comparisons always require sign extension.
1985+
if (ISD::isSignedIntSetCC(CCCode)) {
1986+
LHS = SExtPromotedInteger(LHS);
1987+
RHS = SExtPromotedInteger(RHS);
1988+
return;
1989+
}
1990+
1991+
assert((ISD::isUnsignedIntSetCC(CCCode) || ISD::isIntEqualitySetCC(CCCode)) &&
1992+
"Unknown integer comparison!");
1993+
1994+
SExtOrZExtPromotedOperands(LHS, RHS);
1995+
}
1996+
19871997
SDValue DAGTypeLegalizer::PromoteIntOp_ANY_EXTEND(SDNode *N) {
19881998
SDValue Op = GetPromotedInteger(N->getOperand(0));
19891999
return DAG.getNode(ISD::ANY_EXTEND, SDLoc(N), N->getValueType(0), Op);

Diff for: ‎llvm/lib/CodeGen/SelectionDAG/LegalizeTypes.h

+1-14
Original file line numberDiff line numberDiff line change
@@ -275,20 +275,6 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
275275
return DAG.getZeroExtendInReg(Op, dl, OldVT);
276276
}
277277

278-
// Get a promoted operand and sign or zero extend it to the final size
279-
// (depending on TargetLoweringInfo::isSExtCheaperThanZExt). For a given
280-
// subtarget and type, the choice of sign or zero-extension will be
281-
// consistent.
282-
SDValue SExtOrZExtPromotedInteger(SDValue Op) {
283-
EVT OldVT = Op.getValueType();
284-
SDLoc DL(Op);
285-
Op = GetPromotedInteger(Op);
286-
if (TLI.isSExtCheaperThanZExt(OldVT, Op.getValueType()))
287-
return DAG.getNode(ISD::SIGN_EXTEND_INREG, DL, Op.getValueType(), Op,
288-
DAG.getValueType(OldVT));
289-
return DAG.getZeroExtendInReg(Op, DL, OldVT);
290-
}
291-
292278
// Promote the given operand V (vector or scalar) according to N's specific
293279
// reduction kind. N must be an integer VECREDUCE_* or VP_REDUCE_*. Returns
294280
// the nominal extension opcode (ISD::(ANY|ZERO|SIGN)_EXTEND) and the
@@ -415,6 +401,7 @@ class LLVM_LIBRARY_VISIBILITY DAGTypeLegalizer {
415401
SDValue PromoteIntOp_VP_STRIDED(SDNode *N, unsigned OpNo);
416402
SDValue PromoteIntOp_VP_SPLICE(SDNode *N, unsigned OpNo);
417403

404+
void SExtOrZExtPromotedOperands(SDValue &LHS, SDValue &RHS);
418405
void PromoteSetCCOperands(SDValue &LHS,SDValue &RHS, ISD::CondCode Code);
419406

420407
//===--------------------------------------------------------------------===//

Diff for: ‎llvm/test/CodeGen/RISCV/fpclamptosat.ll

-1
Original file line numberDiff line numberDiff line change
@@ -2812,7 +2812,6 @@ define i16 @utesth_f16i16_mm(half %x) {
28122812
; RV64-NEXT: .cfi_offset ra, -8
28132813
; RV64-NEXT: call __extendhfsf2
28142814
; RV64-NEXT: fcvt.lu.s a0, fa0, rtz
2815-
; RV64-NEXT: sext.w a0, a0
28162815
; RV64-NEXT: lui a1, 16
28172816
; RV64-NEXT: addiw a1, a1, -1
28182817
; RV64-NEXT: bltu a0, a1, .LBB43_2

Diff for: ‎llvm/test/CodeGen/RISCV/rvv/fpclamptosat_vec.ll

+42-40
Original file line numberDiff line numberDiff line change
@@ -4827,10 +4827,10 @@ define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) {
48274827
; CHECK-NOV-NEXT: mv s0, a0
48284828
; CHECK-NOV-NEXT: fmv.w.x fa0, a1
48294829
; CHECK-NOV-NEXT: call __extendhfsf2
4830-
; CHECK-NOV-NEXT: fmv.s fs5, fa0
4830+
; CHECK-NOV-NEXT: fmv.s fs6, fa0
48314831
; CHECK-NOV-NEXT: fmv.w.x fa0, s7
48324832
; CHECK-NOV-NEXT: call __extendhfsf2
4833-
; CHECK-NOV-NEXT: fmv.s fs6, fa0
4833+
; CHECK-NOV-NEXT: fmv.s fs5, fa0
48344834
; CHECK-NOV-NEXT: fmv.w.x fa0, s6
48354835
; CHECK-NOV-NEXT: call __extendhfsf2
48364836
; CHECK-NOV-NEXT: fmv.s fs4, fa0
@@ -4846,54 +4846,36 @@ define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) {
48464846
; CHECK-NOV-NEXT: fmv.w.x fa0, s2
48474847
; CHECK-NOV-NEXT: call __extendhfsf2
48484848
; CHECK-NOV-NEXT: fmv.s fs0, fa0
4849-
; CHECK-NOV-NEXT: fcvt.lu.s s2, fs6, rtz
4850-
; CHECK-NOV-NEXT: fcvt.lu.s a0, fs5, rtz
48514849
; CHECK-NOV-NEXT: fmv.w.x fa0, s1
4852-
; CHECK-NOV-NEXT: sext.w s1, a0
4850+
; CHECK-NOV-NEXT: fcvt.lu.s s1, fs6, rtz
48534851
; CHECK-NOV-NEXT: call __extendhfsf2
48544852
; CHECK-NOV-NEXT: fcvt.lu.s a0, fa0, rtz
4855-
; CHECK-NOV-NEXT: sext.w a0, a0
48564853
; CHECK-NOV-NEXT: lui a1, 16
48574854
; CHECK-NOV-NEXT: addiw a1, a1, -1
4858-
; CHECK-NOV-NEXT: bltu a0, a1, .LBB43_2
4855+
; CHECK-NOV-NEXT: bgeu a0, a1, .LBB43_10
48594856
; CHECK-NOV-NEXT: # %bb.1: # %entry
4860-
; CHECK-NOV-NEXT: mv a0, a1
4857+
; CHECK-NOV-NEXT: fcvt.lu.s a2, fs5, rtz
4858+
; CHECK-NOV-NEXT: bgeu s1, a1, .LBB43_11
48614859
; CHECK-NOV-NEXT: .LBB43_2: # %entry
48624860
; CHECK-NOV-NEXT: fcvt.lu.s a3, fs4, rtz
4863-
; CHECK-NOV-NEXT: sext.w a2, s2
4864-
; CHECK-NOV-NEXT: bltu s1, a1, .LBB43_4
4865-
; CHECK-NOV-NEXT: # %bb.3: # %entry
4866-
; CHECK-NOV-NEXT: mv s1, a1
4867-
; CHECK-NOV-NEXT: .LBB43_4: # %entry
4861+
; CHECK-NOV-NEXT: bgeu a2, a1, .LBB43_12
4862+
; CHECK-NOV-NEXT: .LBB43_3: # %entry
48684863
; CHECK-NOV-NEXT: fcvt.lu.s a4, fs3, rtz
4869-
; CHECK-NOV-NEXT: sext.w a3, a3
4870-
; CHECK-NOV-NEXT: bltu a2, a1, .LBB43_6
4871-
; CHECK-NOV-NEXT: # %bb.5: # %entry
4872-
; CHECK-NOV-NEXT: mv a2, a1
4873-
; CHECK-NOV-NEXT: .LBB43_6: # %entry
4864+
; CHECK-NOV-NEXT: bgeu a3, a1, .LBB43_13
4865+
; CHECK-NOV-NEXT: .LBB43_4: # %entry
48744866
; CHECK-NOV-NEXT: fcvt.lu.s a5, fs2, rtz
4875-
; CHECK-NOV-NEXT: sext.w a4, a4
4876-
; CHECK-NOV-NEXT: bltu a3, a1, .LBB43_8
4877-
; CHECK-NOV-NEXT: # %bb.7: # %entry
4878-
; CHECK-NOV-NEXT: mv a3, a1
4879-
; CHECK-NOV-NEXT: .LBB43_8: # %entry
4867+
; CHECK-NOV-NEXT: bgeu a4, a1, .LBB43_14
4868+
; CHECK-NOV-NEXT: .LBB43_5: # %entry
48804869
; CHECK-NOV-NEXT: fcvt.lu.s a6, fs1, rtz
4881-
; CHECK-NOV-NEXT: sext.w a5, a5
4882-
; CHECK-NOV-NEXT: bltu a4, a1, .LBB43_10
4883-
; CHECK-NOV-NEXT: # %bb.9: # %entry
4884-
; CHECK-NOV-NEXT: mv a4, a1
4885-
; CHECK-NOV-NEXT: .LBB43_10: # %entry
4886-
; CHECK-NOV-NEXT: fcvt.lu.s a7, fs0, rtz
4887-
; CHECK-NOV-NEXT: sext.w a6, a6
48884870
; CHECK-NOV-NEXT: bgeu a5, a1, .LBB43_15
4889-
; CHECK-NOV-NEXT: # %bb.11: # %entry
4890-
; CHECK-NOV-NEXT: sext.w a7, a7
4871+
; CHECK-NOV-NEXT: .LBB43_6: # %entry
4872+
; CHECK-NOV-NEXT: fcvt.lu.s a7, fs0, rtz
48914873
; CHECK-NOV-NEXT: bgeu a6, a1, .LBB43_16
4892-
; CHECK-NOV-NEXT: .LBB43_12: # %entry
4893-
; CHECK-NOV-NEXT: bltu a7, a1, .LBB43_14
4894-
; CHECK-NOV-NEXT: .LBB43_13: # %entry
4874+
; CHECK-NOV-NEXT: .LBB43_7: # %entry
4875+
; CHECK-NOV-NEXT: bltu a7, a1, .LBB43_9
4876+
; CHECK-NOV-NEXT: .LBB43_8: # %entry
48954877
; CHECK-NOV-NEXT: mv a7, a1
4896-
; CHECK-NOV-NEXT: .LBB43_14: # %entry
4878+
; CHECK-NOV-NEXT: .LBB43_9: # %entry
48974879
; CHECK-NOV-NEXT: sh a7, 14(s0)
48984880
; CHECK-NOV-NEXT: sh a6, 12(s0)
48994881
; CHECK-NOV-NEXT: sh a5, 10(s0)
@@ -4920,14 +4902,34 @@ define <8 x i16> @utesth_f16i16_mm(<8 x half> %x) {
49204902
; CHECK-NOV-NEXT: fld fs6, 0(sp) # 8-byte Folded Reload
49214903
; CHECK-NOV-NEXT: addi sp, sp, 128
49224904
; CHECK-NOV-NEXT: ret
4905+
; CHECK-NOV-NEXT: .LBB43_10: # %entry
4906+
; CHECK-NOV-NEXT: mv a0, a1
4907+
; CHECK-NOV-NEXT: fcvt.lu.s a2, fs5, rtz
4908+
; CHECK-NOV-NEXT: bltu s1, a1, .LBB43_2
4909+
; CHECK-NOV-NEXT: .LBB43_11: # %entry
4910+
; CHECK-NOV-NEXT: mv s1, a1
4911+
; CHECK-NOV-NEXT: fcvt.lu.s a3, fs4, rtz
4912+
; CHECK-NOV-NEXT: bltu a2, a1, .LBB43_3
4913+
; CHECK-NOV-NEXT: .LBB43_12: # %entry
4914+
; CHECK-NOV-NEXT: mv a2, a1
4915+
; CHECK-NOV-NEXT: fcvt.lu.s a4, fs3, rtz
4916+
; CHECK-NOV-NEXT: bltu a3, a1, .LBB43_4
4917+
; CHECK-NOV-NEXT: .LBB43_13: # %entry
4918+
; CHECK-NOV-NEXT: mv a3, a1
4919+
; CHECK-NOV-NEXT: fcvt.lu.s a5, fs2, rtz
4920+
; CHECK-NOV-NEXT: bltu a4, a1, .LBB43_5
4921+
; CHECK-NOV-NEXT: .LBB43_14: # %entry
4922+
; CHECK-NOV-NEXT: mv a4, a1
4923+
; CHECK-NOV-NEXT: fcvt.lu.s a6, fs1, rtz
4924+
; CHECK-NOV-NEXT: bltu a5, a1, .LBB43_6
49234925
; CHECK-NOV-NEXT: .LBB43_15: # %entry
49244926
; CHECK-NOV-NEXT: mv a5, a1
4925-
; CHECK-NOV-NEXT: sext.w a7, a7
4926-
; CHECK-NOV-NEXT: bltu a6, a1, .LBB43_12
4927+
; CHECK-NOV-NEXT: fcvt.lu.s a7, fs0, rtz
4928+
; CHECK-NOV-NEXT: bltu a6, a1, .LBB43_7
49274929
; CHECK-NOV-NEXT: .LBB43_16: # %entry
49284930
; CHECK-NOV-NEXT: mv a6, a1
4929-
; CHECK-NOV-NEXT: bgeu a7, a1, .LBB43_13
4930-
; CHECK-NOV-NEXT: j .LBB43_14
4931+
; CHECK-NOV-NEXT: bgeu a7, a1, .LBB43_8
4932+
; CHECK-NOV-NEXT: j .LBB43_9
49314933
;
49324934
; CHECK-V-LABEL: utesth_f16i16_mm:
49334935
; CHECK-V: # %bb.0: # %entry

Diff for: ‎llvm/test/CodeGen/RISCV/rvv/get_vector_length.ll

+16-36
Original file line numberDiff line numberDiff line change
@@ -52,47 +52,27 @@ define i32 @vector_length_i16_fixed(i16 zeroext %tc) {
5252
}
5353

5454
define i32 @vector_length_i32_fixed(i32 zeroext %tc) {
55-
; RV32-LABEL: vector_length_i32_fixed:
56-
; RV32: # %bb.0:
57-
; RV32-NEXT: li a1, 2
58-
; RV32-NEXT: bltu a0, a1, .LBB4_2
59-
; RV32-NEXT: # %bb.1:
60-
; RV32-NEXT: li a0, 2
61-
; RV32-NEXT: .LBB4_2:
62-
; RV32-NEXT: ret
63-
;
64-
; RV64-LABEL: vector_length_i32_fixed:
65-
; RV64: # %bb.0:
66-
; RV64-NEXT: sext.w a0, a0
67-
; RV64-NEXT: li a1, 2
68-
; RV64-NEXT: bltu a0, a1, .LBB4_2
69-
; RV64-NEXT: # %bb.1:
70-
; RV64-NEXT: li a0, 2
71-
; RV64-NEXT: .LBB4_2:
72-
; RV64-NEXT: ret
55+
; CHECK-LABEL: vector_length_i32_fixed:
56+
; CHECK: # %bb.0:
57+
; CHECK-NEXT: li a1, 2
58+
; CHECK-NEXT: bltu a0, a1, .LBB4_2
59+
; CHECK-NEXT: # %bb.1:
60+
; CHECK-NEXT: li a0, 2
61+
; CHECK-NEXT: .LBB4_2:
62+
; CHECK-NEXT: ret
7363
%a = call i32 @llvm.experimental.get.vector.length.i32(i32 %tc, i32 2, i1 false)
7464
ret i32 %a
7565
}
7666

7767
define i32 @vector_length_XLen_fixed(iXLen zeroext %tc) {
78-
; RV32-LABEL: vector_length_XLen_fixed:
79-
; RV32: # %bb.0:
80-
; RV32-NEXT: li a1, 2
81-
; RV32-NEXT: bltu a0, a1, .LBB5_2
82-
; RV32-NEXT: # %bb.1:
83-
; RV32-NEXT: li a0, 2
84-
; RV32-NEXT: .LBB5_2:
85-
; RV32-NEXT: ret
86-
;
87-
; RV64-LABEL: vector_length_XLen_fixed:
88-
; RV64: # %bb.0:
89-
; RV64-NEXT: sext.w a0, a0
90-
; RV64-NEXT: li a1, 2
91-
; RV64-NEXT: bltu a0, a1, .LBB5_2
92-
; RV64-NEXT: # %bb.1:
93-
; RV64-NEXT: li a0, 2
94-
; RV64-NEXT: .LBB5_2:
95-
; RV64-NEXT: ret
68+
; CHECK-LABEL: vector_length_XLen_fixed:
69+
; CHECK: # %bb.0:
70+
; CHECK-NEXT: li a1, 2
71+
; CHECK-NEXT: bltu a0, a1, .LBB5_2
72+
; CHECK-NEXT: # %bb.1:
73+
; CHECK-NEXT: li a0, 2
74+
; CHECK-NEXT: .LBB5_2:
75+
; CHECK-NEXT: ret
9676
%a = call i32 @llvm.experimental.get.vector.length.iXLen(iXLen %tc, i32 2, i1 false)
9777
ret i32 %a
9878
}

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