Skip to content

Commit eaea460

Browse files
stuijstuij
committed
[AArch64] lower abs intrinsic to new ABS instruction in SelDag
When feature CSSC is available, the SelectionDag abs intrinsic should map to the new scalar ABS instruction. Additionally, the SIMDTwoScalarD tablegen defm includes a pattern match for scalar i64, which we don't want to use when CSSC is enabled. spec: https://developer.arm.com/documentation/ddi0602/2022-09/Base-Instructions/ABS--Absolute-value- Reviewed By: lenary Differential Revision: https://reviews.llvm.org/D138812
1 parent 9f85af5 commit eaea460

File tree

4 files changed

+55
-23
lines changed

4 files changed

+55
-23
lines changed

‎llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

Lines changed: 8 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -545,21 +545,26 @@ AArch64TargetLowering::AArch64TargetLowering(const TargetMachine &TM,
545545
setOperationAction(ISD::CTPOP, MVT::i32, Legal);
546546
setOperationAction(ISD::CTPOP, MVT::i64, Legal);
547547
setOperationAction(ISD::CTPOP, MVT::i128, Expand);
548+
548549
setOperationAction(ISD::PARITY, MVT::i128, Expand);
550+
549551
setOperationAction(ISD::CTTZ, MVT::i32, Legal);
550552
setOperationAction(ISD::CTTZ, MVT::i64, Legal);
551553
setOperationAction(ISD::CTTZ, MVT::i128, Expand);
554+
555+
setOperationAction(ISD::ABS, MVT::i32, Legal);
556+
setOperationAction(ISD::ABS, MVT::i64, Legal);
552557
} else {
553558
setOperationAction(ISD::CTPOP, MVT::i32, Custom);
554559
setOperationAction(ISD::CTPOP, MVT::i64, Custom);
555560
setOperationAction(ISD::CTPOP, MVT::i128, Custom);
556561

557562
setOperationAction(ISD::PARITY, MVT::i64, Custom);
558563
setOperationAction(ISD::PARITY, MVT::i128, Custom);
559-
}
560564

561-
setOperationAction(ISD::ABS, MVT::i32, Custom);
562-
setOperationAction(ISD::ABS, MVT::i64, Custom);
565+
setOperationAction(ISD::ABS, MVT::i32, Custom);
566+
setOperationAction(ISD::ABS, MVT::i64, Custom);
567+
}
563568

564569
setOperationAction(ISD::SDIVREM, MVT::i32, Expand);
565570
setOperationAction(ISD::SDIVREM, MVT::i64, Expand);

‎llvm/lib/Target/AArch64/AArch64InstrFormats.td

Lines changed: 4 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -7265,12 +7265,15 @@ multiclass SIMDFPCmpTwoScalar<bit U, bit S, bits<5> opc, string asm,
72657265
}
72667266

72677267
multiclass SIMDTwoScalarD<bit U, bits<5> opc, string asm,
7268-
SDPatternOperator OpNode = null_frag> {
7268+
SDPatternOperator OpNode = null_frag,
7269+
list<Predicate> preds = []> {
72697270
def v1i64 : BaseSIMDTwoScalar<U, 0b11, 0b00, opc, FPR64, FPR64, asm,
72707271
[(set (v1i64 FPR64:$Rd), (OpNode (v1i64 FPR64:$Rn)))]>;
72717272

7273+
let Predicates = preds in {
72727274
def : Pat<(i64 (OpNode (i64 FPR64:$Rn))),
72737275
(!cast<Instruction>(NAME # "v1i64") FPR64:$Rn)>;
7276+
}
72747277
}
72757278

72767279
let mayRaiseFPException = 1, Uses = [FPCR] in

‎llvm/lib/Target/AArch64/AArch64InstrInfo.td

Lines changed: 4 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -115,8 +115,9 @@ def HasDotProd : Predicate<"Subtarget->hasDotProd()">,
115115
AssemblerPredicateWithAll<(all_of FeatureDotProd), "dotprod">;
116116
def HasCRC : Predicate<"Subtarget->hasCRC()">,
117117
AssemblerPredicateWithAll<(all_of FeatureCRC), "crc">;
118-
def HasCSSC : Predicate<"Subtarget->hasCSSC()">,
118+
def HasCSSC : Predicate<"Subtarget->hasCSSC()">,
119119
AssemblerPredicateWithAll<(all_of FeatureCSSC), "cssc">;
120+
def HasNoCSSC : Predicate<"!Subtarget->hasCSSC()">;
120121
def HasLSE : Predicate<"Subtarget->hasLSE()">,
121122
AssemblerPredicateWithAll<(all_of FeatureLSE), "lse">;
122123
def HasNoLSE : Predicate<"!Subtarget->hasLSE()">;
@@ -5092,7 +5093,7 @@ def : Pat<(i64 (int_aarch64_neon_sqsub (i64 FPR64:$Rd),
50925093
// Advanced SIMD two scalar instructions.
50935094
//===----------------------------------------------------------------------===//
50945095

5095-
defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", abs>;
5096+
defm ABS : SIMDTwoScalarD< 0, 0b01011, "abs", abs, [HasNoCSSC]>;
50965097
defm CMEQ : SIMDCmpTwoScalarD< 0, 0b01001, "cmeq", AArch64cmeqz>;
50975098
defm CMGE : SIMDCmpTwoScalarD< 1, 0b01000, "cmge", AArch64cmgez>;
50985099
defm CMGT : SIMDCmpTwoScalarD< 0, 0b01000, "cmgt", AArch64cmgtz>;
@@ -8554,7 +8555,7 @@ defm RCWSWP : ReadCheckWriteOperation<0b010, "swp">;
85548555
//===----------------------------------------------------------------------===//
85558556
// General Data-Processing Instructions (FEAT_V94_DP)
85568557
//===----------------------------------------------------------------------===//
8557-
defm ABS : OneOperandData<0b001000, "abs">, Requires<[HasCSSC]>;
8558+
defm ABS : OneOperandData<0b001000, "abs", abs>, Requires<[HasCSSC]>;
85588559
defm CNT : OneOperandData<0b000111, "cnt", ctpop>, Requires<[HasCSSC]>;
85598560
defm CTZ : OneOperandData<0b000110, "ctz", cttz>, Requires<[HasCSSC]>;
85608561

‎llvm/test/CodeGen/AArch64/iabs.ll

Lines changed: 39 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,12 +1,20 @@
1-
; RUN: llc < %s -mtriple=arm64-eabi -aarch64-neon-syntax=apple | FileCheck %s
1+
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
2+
; RUN: llc < %s -mtriple=arm64-eabi | FileCheck %s
3+
; RUN: llc < %s -mtriple=arm64-eabi -mattr=+cssc | FileCheck %s -check-prefix=CHECK-CSSC
24

35
define i8 @test_i8(i8 %a) nounwind {
46
; CHECK-LABEL: test_i8:
57
; CHECK: // %bb.0:
6-
; CHECK-NEXT: sxtb w8, w0
7-
; CHECK-NEXT: cmp w8, #0
8-
; CHECK-NEXT: cneg w0, w8, mi
9-
; CHECK-NEXT: ret
8+
; CHECK-NEXT: sxtb w8, w0
9+
; CHECK-NEXT: cmp w8, #0
10+
; CHECK-NEXT: cneg w0, w8, mi
11+
; CHECK-NEXT: ret
12+
;
13+
; CHECK-CSSC-LABEL: test_i8:
14+
; CHECK-CSSC: // %bb.0:
15+
; CHECK-CSSC-NEXT: sxtb w8, w0
16+
; CHECK-CSSC-NEXT: abs w0, w8
17+
; CHECK-CSSC-NEXT: ret
1018
%tmp1neg = sub i8 0, %a
1119
%b = icmp sgt i8 %a, -1
1220
%abs = select i1 %b, i8 %a, i8 %tmp1neg
@@ -16,10 +24,16 @@ define i8 @test_i8(i8 %a) nounwind {
1624
define i16 @test_i16(i16 %a) nounwind {
1725
; CHECK-LABEL: test_i16:
1826
; CHECK: // %bb.0:
19-
; CHECK-NEXT: sxth w8, w0
20-
; CHECK-NEXT: cmp w8, #0
21-
; CHECK-NEXT: cneg w0, w8, mi
22-
; CHECK-NEXT: ret
27+
; CHECK-NEXT: sxth w8, w0
28+
; CHECK-NEXT: cmp w8, #0
29+
; CHECK-NEXT: cneg w0, w8, mi
30+
; CHECK-NEXT: ret
31+
;
32+
; CHECK-CSSC-LABEL: test_i16:
33+
; CHECK-CSSC: // %bb.0:
34+
; CHECK-CSSC-NEXT: sxth w8, w0
35+
; CHECK-CSSC-NEXT: abs w0, w8
36+
; CHECK-CSSC-NEXT: ret
2337
%tmp1neg = sub i16 0, %a
2438
%b = icmp sgt i16 %a, -1
2539
%abs = select i1 %b, i16 %a, i16 %tmp1neg
@@ -29,9 +43,14 @@ define i16 @test_i16(i16 %a) nounwind {
2943
define i32 @test_i32(i32 %a) nounwind {
3044
; CHECK-LABEL: test_i32:
3145
; CHECK: // %bb.0:
32-
; CHECK-NEXT: cmp w0, #0
33-
; CHECK-NEXT: cneg w0, w0, mi
34-
; CHECK-NEXT: ret
46+
; CHECK-NEXT: cmp w0, #0
47+
; CHECK-NEXT: cneg w0, w0, mi
48+
; CHECK-NEXT: ret
49+
;
50+
; CHECK-CSSC-LABEL: test_i32:
51+
; CHECK-CSSC: // %bb.0:
52+
; CHECK-CSSC-NEXT: abs w0, w0
53+
; CHECK-CSSC-NEXT: ret
3554
%tmp1neg = sub i32 0, %a
3655
%b = icmp sgt i32 %a, -1
3756
%abs = select i1 %b, i32 %a, i32 %tmp1neg
@@ -41,12 +60,16 @@ define i32 @test_i32(i32 %a) nounwind {
4160
define i64 @test_i64(i64 %a) nounwind {
4261
; CHECK-LABEL: test_i64:
4362
; CHECK: // %bb.0:
44-
; CHECK-NEXT: cmp x0, #0
45-
; CHECK-NEXT: cneg x0, x0, mi
46-
; CHECK-NEXT: ret
63+
; CHECK-NEXT: cmp x0, #0
64+
; CHECK-NEXT: cneg x0, x0, mi
65+
; CHECK-NEXT: ret
66+
;
67+
; CHECK-CSSC-LABEL: test_i64:
68+
; CHECK-CSSC: // %bb.0:
69+
; CHECK-CSSC-NEXT: abs x0, x0
70+
; CHECK-CSSC-NEXT: ret
4771
%tmp1neg = sub i64 0, %a
4872
%b = icmp sgt i64 %a, -1
4973
%abs = select i1 %b, i64 %a, i64 %tmp1neg
5074
ret i64 %abs
5175
}
52-

0 commit comments

Comments
 (0)